24AA02E48/24AA025E48/ 24AA02E64/24AA025E64 2 2K I C Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity Device Selection Table VCC Max. Clock Node Part Number Temp. Ranges Cascadable Page Size Range Frequency Address 24AA02E48 1.7V-5.5V 400kHz(1) I No 8-Byte EUI-48™ 24AA025E48 1.7V-5.5V 400kHz(1) I Yes 16-Byte EUI-48™ 24AA02E64 1.7V-5.5V 400kHz(1) I No 8-Byte EUI-64™ 24AA025E64 1.7V-5.5V 400kHz(1) I Yes 16-Byte EUI-64™ Note 1: 100kHz for VCC <2.5V Features Description The Microchip Technology Inc. • Pre-Programmed Globally Unique, 48-bit or 64-bit 24AA02E48/24AA025E48/24AA02E64/24AA025E64 Node Address (24AA02XEXX) is a 2Kbit Electrically Erasable • Compatible with EUI-48™ and EUI-64™ PROM. The device is organized as two blocks of • Single Supply with Operation Down to 1.7V 128x8-bit memory with a 2-wire serial interface. • Low-Power CMOS Technology: Low-voltage design permits operation down to 1.7V, - Read current 1mA, maximum with maximum standby currents of only 1µA for - Standby current: 1µA, maximum (I-Temp.) I-Temp. and 5µA for E-Temp., as well as a maximum active current of 1mA. The 24AA02XEXX also has a 5µA, maximum (E-Temp.) page write capability for up to eight bytes of data • 2-Wire Serial Interface, I2C Compatible (16bytes on the 24AA025E48/24AA025E64). The • Schmitt Trigger Inputs for Noise Suppression 24AA02XEXX is available in the standard 8-pin SOIC, 5-lead SOT-23, and 6-lead SOT-23 packages. • Output Slope Control to Eliminate Ground Bounce • 100kHz and 400kHz Clock Compatibility Note: 24AA02XEXX is used in this document as • Page Write Time 3ms, typical a generic part number for the • Self-Timed Erase/Write Cycle 24AA02E48/24AA025E48/24AA02E64/2 4AA025E64 devices. • Page Write Buffer: - 8-byte page (24AA02E48/24AA02E64) Packages (24AA02E48/24AA02E64) - 16-byte page (24AA025E48/24AA025E64) SOT-23 SOIC • ESD Protection >4,000V • More than 1 Million Erase/Write Cycles SCL 1 5 NC NC 1 8 VCC • Data Retention >200 Years NC 2 7 NC • Factory Programming Available Vss 2 NC 3 6 SCL • Available Packages: SDA 3 4 Vcc VSS 4 5 SDA - 8-lead SOIC and 5-lead SOT-23 (24AA02E48/24AA02E64) - 8-lead SOIC and 6-lead SOT-23 Packages (24AA025E48/24AA025E64) (24AA025E48/24AA025E64) • RoHS Compliant SOT-23 SOIC • Available for Extended Temperature Ranges: SCL 1 6 VCC A0 1 8 VCC - Industrial (I): -40°C to +85°C A1 2 7 NC - Automotive (E): -40°C to +125°C VSS 2 5 A0 A2 3 6 SCL SDA 3 4 A1 VSS 4 5 SDA  2008-2018 Microchip Technology Inc. DS20002124H-page 1

24AA02E48/24AA025E48/24AA02E64/24AA025E64 Block Diagram A0(1)A1(1)A2(1) HV Generator I/O Memory C Loongtircol CLoongtircol XDEC EEPROM Array SDASCL Write-Protect VCC Circuitry YDEC VSS Sense Amp. R/W Control Note1: Pins A0, A1 and A2 are not available on the 24AA02E48/24AA02E64.  2008-2018 Microchip Technology Inc. DS20002124H-page 2

24AA02E48/24AA025E48/24AA02E64/24AA025E64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS..........................................................................................................-0.3V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V DC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. D1 VIH High-Level Input Voltage 0.7VCC — — V D2 VIL Low-Level Input Voltage — — 0.3VCC V D3 VHYS Hysteresis of Schmitt 0.05VCC — — V Note Trigger Inputs D4 VOL Low-Level Output Voltage — — 0.40 V IOL = 3.0mA, VCC=2.5V D5 ILI Input Leakage Current — — ±1 µA VIN = VSS or VCC D6 ILO Output Leakage Current — — ±1 µA VOUT = VSS or VCC D7 CIN, Pin Capacitance — — 10 pF VCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, FCLK = 1MHz D8 ICCWRITE Operating Current — 0.1 3 mA VCC = 5.5V, SCL = 400kHz D9 ICCREAD — 0.05 1 mA D10 ICCS Standby Current — 0.01 1 µA Industrial (I) SDA = SCL = VCC — 0.01 5 µA Automotive (E) SDA = SCL = VCC Note: This parameter is periodically sampled and not 100% tested.  2008-2018 Microchip Technology Inc. DS20002124H-page 3

24AA02E48/24AA025E48/24AA02E64/24AA025E64 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. 1 FCLK Clock Frequency — — 400 kHz 2.5V  VCC  5.5V — — 100 kHz 1.7V  VCC  2.5V 2 THIGH Clock High Time 600 — — ns 2.5V  VCC  5.5V 4000 — — ns 1.7V  VCC  2.5V 3 TLOW Clock Low Time 1300 — — ns 2.5V  VCC  5.5V 4700 — — ns 1.7V  VCC  2.5V 4 TR SDA and SCL Rise Time — — 300 ns 2.5V  VCC  5.5V (Note1) (Note1) — — 1000 ns 1.7V  VCC  2.5V (Note1) 5 TF SDA and SCL Fall Time — — 300 ns Note1 6 THD:STA Start Condition Hold Time 600 — — ns 2.5V  VCC  5.5V 4000 — — ns 1.7V  VCC  2.5V 7 TSU:STA Start Condition Setup Time 600 — — ns 2.5V  VCC  5.5V 4700 — — ns 1.7V  VCC  2.5V 8 THD:DAT Data Input Hold Time 0 — — ns Note2 9 TSU:DAT Data Input Setup Time 100 — — ns 2.5V  VCC  5.5V 250 — — ns 1.7V  VCC  2.5V 10 TSU:STO Stop Condition Setup Time 600 — — ns 2.5V  VCC  5.5V 4000 — — ns 1.7V  VCC  2.5V 11 TAA Output Valid from Clock — — 900 ns 2.5V  VCC  5.5V (Note2) — — 3500 ns 1.7V  VCC  2.5V 12 TBUF Bus Free Time: Bus time 1300 — — ns 2.5V  VCC  5.5V must be free before a new 4700 — — ns 1.7V  VCC  2.5V transmission can start 13 TOF Output Fall Time from VIH — — 250 ns 2.5V  VCC  5.5V Minimum to VIL Maximum — — 250 ns 1.7V  VCC  2.5V 14 TSP Input Filter Spike — — 50 ns Notes1 and3 Suppression (SDA and SCL pins) 15 TWC Write Cycle Time (byte or — — 5 ms page) 16 Endurance 1M — — cycles 25°C (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at www.microchip.com.  2008-2018 Microchip Technology Inc. DS20002124H-page 4

24AA02E48/24AA025E48/24AA02E64/24AA025E64 FIGURE 1-1: BUS TIMING DATA 5 4 2 3 SCL 7 8 9 10 6 SDA In 14 11 12 SDA Out FIGURE 1-2: BUS TIMING START/STOP D3 SCL 6 7 10 SDA Start Stop  2008-2018 Microchip Technology Inc. DS20002124H-page 5

24AA02E48/24AA025E48/24AA02E64/24AA025E64 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE Name SOIC 5-Pin SOT-23 6-Pin SOT-23 Description A0 1 — 5 Chip Address Input(1) A1 2 — 4 Chip Address Input(1) A2 3 — — Chip Address Input(1) VSS 4 2 2 Ground SDA 5 3 3 Serial Address/Data I/O SCL 6 1 1 Serial Clock NC 7 5 — Not Connected VCC 8 4 6 +1.7V to 5.5V Power Supply Note 1: Chip address inputs A0, A1 and A2 are not connected on the 24AA02E48/24AA02E64. 2.1 Serial Address/Data Input/Output (SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an open-drain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10k for 100kHz, 2k for 400kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating Start and Stop conditions. 2.2 Serial Clock (SCL) The SCL input is used to synchronize the data transfer to and from the device. 2.3 A0, A1, A2 Chip Address Inputs The A0, A1 and A2 pins are not used by the 24AA02E48/24AA02E64. They may be left floating or tied to either VSS or VCC. For the 24AA025E48/24AA025E64, the levels on the A0, A1 and A2 inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. For the 6-lead SOT-23 package, pin A2 is not connected and its corresponding bit in the slave address should always be set to ‘0’. Up to eight 24AA025E48/24AA025E64 devices (four for the SOT-23 package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VSS or VCC.  2008-2018 Microchip Technology Inc. DS20002124H-page 6

24AA02E48/24AA025E48/24AA02E64/24AA025E64 3.0 FUNCTIONAL DESCRIPTION 4.4 Data Valid (D) The 24AA02XEXX supports a bidirectional, 2-wire bus The state of the data line represents valid data when, and data transmission protocol. A device that sends after a Start condition, the data line is stable for the data onto the bus is defined as transmitter, while a duration of the high period of the clock signal. device receiving data is defined as a receiver. The bus The data on the line must be changed during the low has to be controlled by a master device which gener- period of the clock signal. There is one clock pulse per ates the Serial Clock (SCL), controls the bus access bit of data. and generates the Start and Stop conditions, while the Each data transfer is initiated with a Start condition and 24AA02XEXX works as slave. Both master and slave terminated with a Stop condition. The number of data can operate as transmitter or receiver, but the master bytes transferred between Start and Stop conditions is device determines which mode is activated. determined by the master device and is, theoretically, unlimited (although only the last sixteen will be stored 4.0 BUS CHARACTERISTICS when doing a write operation). When an overwrite does occur, it will replace data in a first-in first-out (FIFO) The following bus protocol has been defined: fashion. • Data transfer may be initiated only when the bus is not busy. 4.5 Acknowledge • During data transfer, the data line must remain stable whenever the clock line is high. Changes in Each receiving device, when addressed, is obliged to the data line while the clock line is high will be generate an acknowledge after the reception of each interpreted as a Start or Stop condition. byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Accordingly, the following bus conditions have been defined (Figure4-1). Note: The 24AA02XEXX does not generate any Acknowledge bits if an internal 4.1 Bus Not Busy (A) programming cycle is in progress. Both data and clock lines remain high. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a 4.2 Start Data Transfer (B) way that the SDA line is stable-low during the high period of the acknowledge related clock pulse. Of A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into (SCL) is high determines a Start condition. All account. During reads, a master must signal an end of commands must be preceded by a Start condition. data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. 4.3 Stop Data Transfer (C) In this case, the slave (24AA02XEXX) will leave the data line high to enable the master to generate the Stop A low-to-high transition of the SDA line while the clock condition. (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change  2008-2018 Microchip Technology Inc. DS20002124H-page 7

24AA02E48/24AA025E48/24AA02E64/24AA025E64 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE ALLOCATION A control byte is the first byte received following the Start condition from the master device. The control byte Read/Write Bit consists of a four-bit control code. For the 24AA02XEXX, this is set as ‘1010’ binary for read and Chip write operations. For the 24AA02E48/24AA02E64 the Select Control Code Bits next three bits of the control byte are “don’t cares”. For the 24AA025E48/24AA025E64, the next three bits S 1 0 1 0 A2*A1*A0*R/W ACK of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA025E48/24AA025E64 devices on the same bus Slave Address and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to Start Bit Acknowledge Bit the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect Note: * Bits A0, A1 and A2 are “don’t cares” for the three Most Significant bits of the word address. the 24AA02E48/24AA02E64. For the 6-pin SOT-23 package, the A2 address pin is not available. During device addressing, the A2 Chip 5.1 Contiguous Addressing Across Select bit should be set to ‘0’. Multiple Devices The last bit of the control byte defines the operation to be performed. When set to ‘1’, a read operation is The Chip Select bits A2, A1 and A0 can be used to selected. When set to ‘0’, a write operation is selected. expand the contiguous address space for up to 16K bits Following the Start condition, the 24AA02XEXX moni- by adding up to eight 24AA025E48/24AA025E64 tors the SDA bus, checking the device type identifier devices on the same bus. In this case, software can being transmitted and, upon a ‘1010’ code, the slave use A0 of the control byte as address bit A8, A1 as device outputs an Acknowledge signal on the SDA line. address bit A9 and A2 as address bit A10. It is not Depending on the state of the R/W bit, the possible to sequentially read across device 24AA02XEXX will select a read or write operation. boundaries. For the SOT-23 package, up to four Control Operation Chip Select R/W 24AA025E48/24AA025E64 devices can be added for Code up to 8K bits of address space. In this case, software Read 1010 Chip Address 1 can us A0 of the control byte as address bit A8, and Write 1010 Chip Address 0 A1 as address bit A9. It is not possible to sequentially read across device boundaries. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte Address Low Byte A A 1 0 1 0 A2*A1*A0*R/W • • • • • • 7 0 Control Chip Code Select bits Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.  2008-2018 Microchip Technology Inc. DS20002124H-page 8

24AA02E48/24AA025E48/24AA02E64/24AA025E64 6.0 WRITE OPERATION The higher-order five bits (four for the 24AA025E48/24AA025E64) of the word address remain constant. If the master should transmit more 6.1 Byte Write than eight words (16 for the Following the Start condition from the master, the 24AA025E48/24AA025E64) prior to generating the device code (four bits), the chip address (three bits) Stop condition, the address counter will roll over and the and the R/W bit which is a logic-low, is placed onto the previously received data will be overwritten. As with the bus by the master transmitter. This indicates to the byte write operation, once the Stop condition is received addressed slave receiver that a byte with a word an internal write cycle will begin (Figure6-2). address will follow once it has generated an Note: Page write operations are limited to Acknowledge bit during the ninth clock cycle. writing bytes within a single physical page Therefore, the next byte transmitted by the master is regardless of the number of bytes the word address and will be written into the Address actually being written. Physical page Pointer of the 24AA02XEXX. After receiving another boundaries start at addresses that are Acknowledge signal from the 24AA02XEXX, the integer multiples of the page buffer size master device will transmit the data word to be written (or ‘page size’) and end at addresses that into the addressed memory location. The are integer multiples of [page size – 1]. If 24AA02XEXX acknowledges again and the master a page write command attempts to write generates a Stop condition. This initiates the internal across a physical page boundary, the write cycle and, during this time, the 24AA02XEXX will result is that the data wraps around to the not generate Acknowledge signals (Figure6-1). beginning of the current page (overwriting data previously stored there), instead of 6.2 Page Write being written to the next page, as might be expected. It is therefore necessary for the The write control byte, word address and the first data application software to prevent page write byte are transmitted to the 24AA02XEXX in the same operations that would attempt to cross a way as in a byte write. However, instead of generating page boundary. a Stop condition, the master transmits up to eight data bytes to the 24AA02XEXX, which are temporarily stored in the on-chip page buffer and will be written into 6.3 Write Protection memory once the master has transmitted a Stop The upper half of the array (80h-FFh) is permanently condition. Upon receipt of each word, the three write-protected. Write operations to this address range lower-order Address Pointer bits (four for the are inhibited. Read operations are not affected. 24AA025E48/24AA025E64) are internally incremented by one. The remaining half of the array (00h-7Fh) can be written to and read from normally. FIGURE 6-1: BYTE WRITE S S Bus Activity T Control Word T Master A Byte Address Data O R P T SDA Line S 1 0 1 0 A2*A1*A0* 0 P A A A Bus Activity C C C Chip K K K Select Bits Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.  2008-2018 Microchip Technology Inc. DS20002124H-page 9

24AA02E48/24AA025E48/24AA02E64/24AA025E64 FIGURE 6-2: PAGE WRITE S S Bus Activity T Control Word T Master AR Byte Address (n) Data (n) Data (n + 1) Data (n + 7) OP T SDA Line S 10 10A*2A*1A*00 P A A A A A Bus Activity Chip C C C C C Select K K K K K Bits Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.  2008-2018 Microchip Technology Inc. DS20002124H-page 10

24AA02E48/24AA025E48/24AA02E64/24AA025E64 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the master can then proceed with the next read or write command. See Figure7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device No Acknowledge (ACK = 0)? Yes Next Operation  2008-2018 Microchip Technology Inc. DS20002124H-page 11

24AA02E48/24AA025E48/24AA02E64/24AA025E64 8.0 READ OPERATION 8.3 Sequential Read Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a operations, with the exception that the R/W bit of the random read, except that once the 24AA02XEXX slave address is set to ‘1’. There are three basic types transmits the first data byte, the master issues an of read operations: current address read, random read acknowledge as opposed to a Stop condition in a and sequential read. random read. This directs the 24AA02XEXX to transmit the next sequentially addressed 8-bit word (Figure8-3). 8.1 Current Address Read To provide sequential reads, the 24AA02XEXX contains an internal Address Pointer that is The 24AA02XEXX contains an address counter that incremented by one upon completion of each opera- maintains the address of the last word accessed, tion. This Address Pointer allows the entire memory internally incremented by one. Therefore, if the contents to be serially read during one operation. previous access (either a read or write operation) was to address ‘n’, the next current address read operation 8.4 Noise Protection would access data from address n+1. Upon receipt of the slave address with R/W bit set to ‘1’, the The 24AA02XEXX employs a VCC threshold detector 24AA02XEXX issues an acknowledge and transmits circuit which disables the internal erase/write logic if the the 8-bit data word. The master will not acknowledge VCC is below 1.5V at nominal conditions. the transfer, but generate a Stop condition, and the The SCL and SDA inputs have Schmitt Trigger and 24AA02XEXX discontinues transmission (Figure8-1). filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24AA02XEXX as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24AA02XEXX will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but generate a Stop condition, and the 24AA02XEXX will discontinue transmission (Figure8-2). FIGURE 8-1: CURRENT ADDRESS READ S Bus Activity T Control S Master A Byte Data (n) T R O T P SDA Line S 1 0 1 0 A2*A1*A0* 1 P A N Bus Activity C o Chip K Select A Bits C K Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.  2008-2018 Microchip Technology Inc. DS20002124H-page 12

24AA02E48/24AA025E48/24AA02E64/24AA025E64 FIGURE 8-2: RANDOM READ S S Bus Activity T Control Word T Control S A A T Master R Byte Address (n) R Byte Data (n) O T T P * * * * ** S 10 1 0A2A1A00 S 1 01 0A2A1A01 P SDA Line A A A N Chip C C Chip C o Select K K Select K Bus Activity Bits Bits A C K Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64. FIGURE 8-3: SEQUENTIAL READ S Bus Activity Control T Master Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x) O P SDA Line 1 P A A A A N Bus Activity C C C C o K K K K A C K  2008-2018 Microchip Technology Inc. DS20002124H-page 13

24AA02E48/24AA025E48/24AA02E64/24AA025E64 9.0 PRE-PROGRAMMED EUI-48™ 9.1.1 ORGANIZATIONALLY UNIQUE OR EUI-64™ NODE ADDRESS IDENTIFIERS (OUIs) Each OUI provides roughly 16M (224) addresses. Once The 24AA02XEXX is programmed at the factory with a the address pool for an OUI is exhausted, Microchip globally unique node address stored in the upper half will acquire a new OUI from IEEE to use for of the array and permanently write-protected. The programming this model. For more information on past remaining 1,024 bits are available for application use. and current OUIs see “Organizationally Unique Identifiers For Preprogrammed EUI-48 and EUI-64 FIGURE 9-1: MEMORY ORGANIZATION Address Devices” Technical Brief (DS90003187). 00h Note: The OUI will change as addresses are Standard EEPROM exhausted. Customers are not guaran- teed to receive a specific OUI and should 80h design their application to accept new OUIs as they are introduced. Write-Protected Node Address Block 9.1.2 EUI-64™ SUPPORT USING THE FFh 24AAXXXE48 The pre-programmed EUI-48 node address of the 24AAXXXE48 can easily be encapsulated at the 9.1 EUI-48™ Node Address application level to form a globally unique, 64-bit node (24AAXXXE48) address for systems utilizing the EUI-64 standard. This The 6-byte EUI-48™ node address value of the is done by adding 0xFFFE between the OUI and the 24AAXXXE48 is stored in array locations 0xFA through Extension Identifier, as shown below. 0xFF, as shown in Figure9-2. The first three bytes are the Organizationally Unique Identifier (OUI) assigned Note: As an alternative, the 24AAXXXE64 to Microchip by the IEEE Registration Authority. The features an EUI-64 node address that can remaining three bytes are the Extension Identifier, and be used in EUI-64 applications directly are generated by Microchip to ensure a globally without the need for encapsulation, unique, 48-bit value. thereby simplifying system software. See Section9.2 “EUI-64™ Node Address (24AAXXXE64)” for details. FIGURE 9-2: EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (24AAXXXE48) 24-bit Organizationally 24-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h Array FAh FFh Address Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56  2008-2018 Microchip Technology Inc. DS20002124H-page 14

24AA02E48/24AA025E48/24AA02E64/24AA025E64 9.2 EUI-64™ Node Address (24AAXXXE64) The 8-byte EUI-64™ node address value of the 24AAXXXE64 is stored in array locations 0xF8 through 0xFF, as shown in Figure9-3. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining five bytes are the Extension Identifier, and are generated by Microchip to ensure a globally unique, 64-bit value. Note: In conformance with IEEE guidelines, Microchip will not use the values 0xFFFE and 0xFFFF for the first two bytes of the EUI-64 Extension Identifier. These two values are specifically reserved to allow applications to encapsulate EUI-48 addresses into EUI-64 addresses. FIGURE 9-3: EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (24AAXXXE64) 24-bit Organizationally 40-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h 78h 90h Array F8h FFh Address Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90  2008-2018 Microchip Technology Inc. DS20002124H-page 15

24AA02E48/24AA025E48/24AA02E64/24AA025E64 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 8-Lead SOIC (3.90 mm) Example XXXXXXXT 24A2E48I XXXXYYWW SN e 3 1 6 2 5 NNN 13F 5-Lead SOT-23 (1-Line Marking) Example XXNN 2K3F 6-Lead SOT-23 (1-Line Marking) Example XXNN HS3F 5-Lead SOT-23 (2-Line Marking) Example XXXXY AAAB6 WWNNN 251L7 6-Lead SOT-23 (2-Line Marking) Example XXXXY AAAC6 WWNNN 251L7 1st Line Marking Code Part Number SOT-23 SOIC I-Temp. E-Temp. I-Temp. E-Temp. 24AA02E48 2KNN(1,2) AABLY(3) 24A2E48I 24A2E48E 24AA025E48 HSNN(1,2) AABMY(3) 4A25E48I 4A25E48E 24AA02E64 AAABY(3) AABNY(3) 24A2E64I 24A2E64E 24AA025E64 AAACY(3) AABPY(3) 4A25E64I 4A25E64E Note 1: NN = Alphanumeric traceability code 2: These parts use the 1-line SOT-23 marking format 3: These parts use the 2-line SOT-23 marking format  2008-2018 Microchip Technology Inc. DS20002124H-page 16

24AA02E48/24AA025E48/24AA02E64/24AA025E64 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 JEDEC® designator for Matte Tin (Sn) *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. Note: For very small packages with no room for the JEDEC® designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2018 Microchip Technology Inc. DS20002124H-page 17

24AA02E48/24AA025E48/24AA02E64/24AA025E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2008-2018 Microchip Technology Inc. DS20002124H-page 18

24AA02E48/24AA025E48/24AA02E64/24AA025E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2008-2018 Microchip Technology Inc. DS20002124H-page 19

24AA02E48/24AA025E48/24AA02E64/24AA025E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2008-2018 Microchip Technology Inc. DS20002124H-page 20

24AA02E48/24AA025E48/24AA02E64/24AA025E64 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A2 A 0.20 C SEATING PLANE A SEE SHEET 2 C A1 SIDE VIEW Microchip Technology Drawing C04-028D [OT] Sheet 1 of(cid:3)(cid:21)  2008-2018 Microchip Technology Inc. DS20002124H-page 21

24AA02E48/24AA025E48/24AA02E64/24AA025E64 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c (cid:84) L L1 VIEW A-A SHEET 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 6 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 - 1.30 Standoff A1 - - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 - 0.60 Footprint L1 0.60 REF Foot Angle (cid:73) 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091D [OT] Sheet 2 of(cid:3)(cid:21)  2008-2018 Microchip Technology Inc. DS20002124H-page 22

24AA02E48/24AA025E48/24AA02E64/24AA025E64 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X5) X 0.60 Contact Pad Length (X5) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091A [OT]  2008-2018 Microchip Technology Inc. DS20002124H-page 23

24AA02E48/24AA025E48/24AA02E64/24AA025E64 6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.15 C A-B D e1 A D E 2 E1 E E1 2 2X 0.15 C D 2X 0.20 C A-B e B 6X b 0.20 C A-B D TOP VIEW A2 A C SEATING PLANE 6X A1 0.10 C SIDE VIEW R1 R L2 c GAUGE PLANE L (cid:300) (L1) END VIEW Microchip Technology Drawing C04-028C (OT) Sheet 1 of 2  2008-2018 Microchip Technology Inc. DS20002124H-page 24

24AA02E48/24AA025E48/24AA02E64/24AA025E64 6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 6 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 1.15 1.30 Standoff A1 0.00 - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 0.45 0.60 Footprint L1 0.60 REF Seating Plane to Gauge Plane L1 0.25 BSC φ Foot Angle 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-028C (OT) Sheet 2 of 2  2008-2018 Microchip Technology Inc. DS20002124H-page 25

24AA02E48/24AA025E48/24AA02E64/24AA025E64 6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging GX Y Z C G G SILK SCREEN X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X3) X 0.60 Contact Pad Length (X3) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2028B (OT)  2008-2018 Microchip Technology Inc. DS20002124H-page 26

24AA02E48/24AA025E48/24AA02E64/24AA025E64 APPENDIX A: REVISION HISTORY Revision A (12/08) Initial release of this document. Revision B (01/09) Removed preliminary status. Revision C (03/10) Added new sections 2.0 through 9.0. Revision D (05/10) Added 24AA025E48 part number and 6-lead SOT-23 package. Revision E (04/13) Added 24AA02E64 and 24AA025E64 part numbers. Revision F (10/14) Added E-temp. option to part numbers. Revision G (08/16) Added new OUI (54-10-EC) to list. Revision H (02/18) Added detailed description of OUIs.  2008-2018 Microchip Technology Inc. DS20002124H-page 27

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24AA02E48/24AA025E48/24AA02E64/24AA025E64 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, • Technical Support application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or Field Application Engineer (FAE) for software support. Local sales offices are also available to help customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2008-2016 Microchip Technology Inc. DS20002124H-page 29

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24AA02E48/24AA025E48/24AA02E64/24AA025E64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. [X]((11)) X /XX a) 24AA02E48-I/SN: 2Kbit, 8-byte page, Serial EEPROM with Device Tape and Reel Temperature Package EUI-48 Node Identity, Option Range 1.7V, Industrial Tempera- Device: 24AA02E48 = 1.7V, 2 Kbit I2C Serial EEPROM ture, SOIC package. b) 24AA02E48T-I/OT: 2Kbit, 8-byte page, with EUI-48™ Node Identity 24AA025E48 = 1.7V, 2 Kbit I2C Serial EEPROM with Serial EEPROM with EUI-48 Node Identity, EUI-48™ Node Identity and Address 1.7V, Tape and Reel, Pins 24AA02E64 = 1.7V, 2 Kbit I2C Serial EEPROM Industrial Temperature, SOT-23 package. with EUI-64™ Node Identity 24AA025E64 = 1.7V, 2 Kbit I2C Serial EEPROM with c) 24AA025E48-I/SN: 2Kbit, 16-byte page, EUI-64™ Node Identity and Address Serial EEPROM with Pins EUI-48 Node Identity, X, 1.7V, Cascadable, Indus- trial Temperature, SOIC Tape and Blank = Standard packaging (tube or tray) package. Reel Option: T = Tape and Reel(1) d) 24AA02E64-I/SN: 2Kbit, 8-byte page, Serial EEPROM with EUI-64 Node Identity, Temperature I = -40°C to +85°C 1.7V, Industrial Tempera- Range: E = -40°C to +125°C ture, SOIC package. e) 24AA02E64T-I/OT: 2Kbit, 8-byte page, Package: SN = Plastic SOIC (3.90 mm body), 8-lead Serial EEPROM with OT = SOT-23 (Tape and Reel only) EUI-64 Node Identity, 1.7V, Tape and Reel, Industrial Temperature, SOT-23 package. f) 24AA025E64-I/SN: 2Kbit, 16-byte page, Serial EEPROM with EUI-64 Node Identity, 1.7V, Cascadable, Indus- trial Temperature, SOIC package. g) 24AA025E48T-E/SN:2Kbit, 16-byte page, Serial EEPROM with EUI-48 Node Identity, 1.7V, Cascadable, Tape and Reel, Automotive Temperature, SOIC pack- age. h) 24AA02E48-E/SN: 2Kbit, 8-byte page, Serial EEPROM with EUI-48 Node Identity, 1.7V, Automotive Tem- perature, SOIC package. i) 24AA025E48T-E/OT:2Kbit, 16-byte page, Serial EEPROM with EUI- 48 Node Identity, 1.7V, Cascadable, Tape and Reel, Automotive Tem- perature, SOT-23 pack- age. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering pur- poses and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2008-2018 Microchip Technology Inc. DS20002124H-page 31

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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT ensure that your application meets with your specifications. logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, MICROCHIP MAKES NO REPRESENTATIONS OR Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK WARRANTIES OF ANY KIND WHETHER EXPRESS OR MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST IMPLIED, WRITTEN OR ORAL, STATUTORY OR logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 OTHERWISE, RELATED TO THE INFORMATION, logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are QUALITY, PERFORMANCE, MERCHANTABILITY OR registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter- Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Microchip Tempe, Arizona; Gresham, Oregon and design centers in California Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip Technology analog products. In addition, Microchip’s quality system for the design Inc., in other countries. and manufacture of development systems is ISO 9001:2000 certified. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2008-2018, Microchip Technology Incorporated, All Rights Reserved. CERTIFIED BY DNV ISBN: 978-1-5224-2735-3 == ISO/TS 16949 ==  2008-2018 Microchip Technology Inc. DS20002124H-page 33

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