24AA024/24LC024/24AA025/24LC025 2 2K I C™ Serial EEPROM Device Selection Table Description: Part VCC Max Temp. Write The Microchip Technology Inc. 24AA024/24LC024/ Number Range Clock Range Protect 24AA025/24LC025 is a 2Kbit Serial Electrically 24AA024 1.7V-5.5V 400kHz(1) I Yes Erasable PROM with a voltage range of 1.7V to 5.5V. 24AA025 1.7V-5.5V 400kHz(1) I No The device is organized as a single block of 256 x8-bit memory with a 2-wire serial interface. Low current 24LC024 2.5V-5.5V 400kHz I Yes design permits operation with typical standby and 24LC025 2.5V-5.5V 400kHz I No active currents of only 1 μA and 1 mA, respectively. Note 1: 100 kHz for VCC < 2.5V The device has a page write capability for up to 16 bytes of data. Functional address lines allow the connection of up to eight 24AA024/24LC024/ Features: 24AA025/24LC025 devices on the same bus for up to • Single supply with operation from 1.7V to 5.5V for 16K bits of contiguous EEPROM memory. The device 24AA024/24AA025 devices, 2.5V for 24LC024/ is available in the standard 8-pin PDIP, 8-pin SOIC 24LC025 devices (3.90 mm), TSSOP, 2x3 DFN and MSOP packages. (cid:129) Low-power CMOS technology: Package Types - Read current 1 mA, typical PDIP, MSOP SOIC, TSSOP - Standby current 1 μA, typical (cid:129) 2-wire serial interface, I 2C™ compatible A0 1 8 VCC A0 1 8 VCC (cid:129) Cascadable up to eight devices A1 2 7 WP A1 2 7 WP (cid:129) Schmitt Trigger inputs for noise suppression A2 3 6 SCL A2 3 6 SCL (cid:129) Output slope control to eliminate ground bounce VSS 4 5 SDAVSS 4 5 SDA (cid:129) 100kHz and 400kHz clock compatibility (cid:129) Page write time 5 ms maximum DFN (cid:129) Self-timed erase/write cycle A0 1 8 VCC (cid:129) 16-byte page write buffer A1 2 7 WP (cid:129) Hardware write-protect on 24XX024 devices A2 3 6 SCL (cid:129) ESD protection >4,000V VSS 4 5 SDA (cid:129) More than 1 million erase/write cycles Note: WP pin is not internally connected on the (cid:129) Data retention >200 years 24XX025. (cid:129) Factory programming available Block Diagram (cid:129) Packages include 8-lead PDIP, SOIC, TSSOP, DFN and MSOP A0 A1 A2 WP* HV Generator (cid:129) Pb-free and RoHS compliant (cid:129) Temperature ranges: I/O Memory - Industrial (I): -40°C to +85°C C Loongtircol CLoongtircol XDEC EEPROM Array SDA SCL Write-Protect VCC Circuitry YDEC VSS Sense Amp. R/W Control © 2007 Microchip Technology Inc. DS21210K-page 1

24AA024/24LC024/24AA025/24LC025 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS All parameters apply across the VCC = 1.7V to 5.5V specified operating ranges unless Industrial (I): TA = -40°C to +85°C otherwise noted. Parameter Symbol Min. Max. Units Conditions SCL and SDA pins: High-level input voltage VIH 0.7 VCC — V — Low-level input voltage VIL — 0.3 VCC V — Hysteresis of Schmitt Trigger inputs VHYS 0.05 VCC — V (Note) Low-level output voltage VOL — 0.40 V IOL = 3.0 mA, VCC = 4.5V IOL = 2.1 mA, VCC = 2.5V Input leakage current ILI — ±1 μA VIN = VSS or VCC Output leakage current ILO — ±1 μA VOUT = VSS or VCC Pin capacitance (all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note) TA = 25°C, FCLK = 1 MHz Operating current ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz ICC Write — 3 mA VCC = 5.5V Standby current ICCS — 1 μA VCC = 5.5V, SDA = SCL = VCC WP = VSS, A0, A1, A2 = VSS Note: This parameter is periodically sampled and not 100% tested. DS21210K-page 2 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 TABLE 1-2: AC CHARACTERISTICS All parameters apply across the specified VCC = 1.7V to 5.5V operating ranges unless otherwise noted. Industrial (I): TA = -40°C to +85°C Vcc = 2.5V - 5.5V STD MODE FAST MODE Parameter Symbol Units Remarks Min. Max. Min. Max. Clock frequency FCLK — 100 — 400 kHz — Clock high time THIGH 4000 — 600 — ns — Clock low time TLOW 4700 — 1300 — ns — SDA and SCL rise time TR — 1000 — 300 ns (Note1) SDA and SCL fall time TF — 300 — 300 ns (Note1) Start condition hold time THD:STA 4000 — 600 — ns After this period the first clock pulse is generated Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated Start condition Data input hold time THD:DAT 0 — 0 — ns (Note2) Data input setup time TSU:DAT 250 — 100 — ns — Stop condition setup time TSU:STO 4000 — 600 — ns — Output valid from clock TAA — 3500 — 900 ns (Note2) Bus free time TBUF 4700 — 1300 — ns Time the bus must be free before a new transmission can start Output fall time from VIH TOF — 250 20 +0.1 250 ns (Note 1), CB ≤ 100 pF minimum to VIL maximum CB Input filter spike suppression TSP — 50 — 50 ns (Note3) (SDA and SCL pins) Write cycle time TWC — 5 — 5 ms Byte or Page mode Endurance 1M — 1M — cycles 25°C, (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com. © 2007 Microchip Technology Inc. DS21210K-page 3

24AA024/24LC024/24AA025/24LC025 FIGURE 1-1: BUS TIMING DATA THIGH TF TR SCL TSU:STA TLOW THD:DAT TSU:DAT TSU:STO SDA THD:STA IN TSP TBUF TAA SDA OUT DS21210K-page 4 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 2.0 PIN DESCRIPTIONS Pin Function Table Name PDIP SOIC TSSOP DFN MSOP Description A0 1 1 1 1 1 Address Pin AO A1 2 2 2 2 2 Address Pin A1 A2 3 3 3 3 3 Address Pin A2 VSS 4 4 4 4 4 Ground SDA 5 5 5 5 5 Serial Address/Data I/O SCL 6 6 6 6 6 Serial Clock WP 7 7 7 7 7 Write-Protect Input VCC 8 8 8 8 8 +1.7 to 5.5V Power Supply 2.1 SDA Serial Data 2.5 Noise Protection SDA is a bidirectional pin used to transfer addresses The 24AA024/24LC024/24AA025/24LC025 employs a and data into and out of the device. It is an open-drain VCC threshold detector circuit which disables the terminal, therefore, the SDA bus requires a pull-up internal erase/write logic if the VCC is below 1.5 volts at resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for nominal conditions. 400kHz). The SCL and SDA inputs have Schmitt Trigger and For normal data transfer, SDA is allowed to change filter circuits which suppress noise spikes to assure only during SCL low. Changes during SCL high are proper device operation, even on a noisy bus. reserved for indicating the Start and Stop conditions. 3.0 FUNCTIONAL DESCRIPTION 2.2 SCL Serial Clock The 24AA024/24LC024/24AA025/24LC025 supports The SCL input is used to synchronize the data transfer a bidirectional, 2-wire bus and data transmission from and to the device. protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data 2.3 A0, A1, A2 is defined as receiver. The bus has to be controlled by a master device which generates the Serial Clock The levels on the A0, A1 and A2 inputs are compared (SCL), controls the bus access and generates the with the corresponding bits in the slave address. The Start and Stop conditions, while the 24AA024/ chip is selected if the compare is true. 24LC024/24AA025/24LC025 works as slave. Both Up to eight 24AA024/24LC024/24AA025/24LC025 master and slave can operate as transmitter or devices may be connected to the same bus by using receiver, but the master device determines which different Chip Select bit combinations. These inputs mode is activated. must be connected to either VCC or VSS. 2.4 WP (24XX024 Only) WP is the hardware write-protect pin. It must be tied to VCC or VSS. If tied to Vcc, hardware write protection is enabled. If WP is tied to Vss, the hardware write protection is disabled. Note that the WP pin is available only on the 24XX024. This pin is not internally connected on the 24LC025. © 2007 Microchip Technology Inc. DS21210K-page 5

24AA024/24LC024/24AA025/24LC025 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per The following bus protocol has been defined: clock pulse. (cid:129) Data transfer may be initiated only when the bus Each data transfer is initiated with a Start condition and is not busy. terminated with a Stop condition. The number of the (cid:129) During data transfer, the data line must remain data bytes transferred between the Start and Stop stable whenever the clock line is high. Changes in conditions is determined by the master device and is, the data line while the clock line is high will be theoretically, unlimited, (though only the last sixteen will interpreted as a Start or Stop condition. be stored when performing a write operation). When an overwrite does occur, it will replace data in a first-in Accordingly, the following bus conditions have been first-out fashion. defined (Figure4-1). 4.5 Acknowledge 4.1 Bus Not Busy (A) Each receiving device, when addressed, is required to Both data and clock lines remain high. generate an acknowledge after the reception of each byte. The master device must generate an extra clock 4.2 Start Data Transfer (B) pulse which is associated with this Acknowledge bit. A high-to-low transition of the SDA line while the clock Note: The 24AA024/24LC024/24AA025/24LC025 (SCL) is high determines a Start condition. All does not generate any Acknowledge bits if commands must be preceded by a Start condition. an internal programming cycle is in progress. 4.3 Stop Data Transfer (C) The device that acknowledges has to pull down the SDA A low-to-high transition of the SDA line while the clock line during the acknowledge clock pulse in such a way (SCL) is high determines a Stop condition. All that the SDA line is stable low during the high period of operations must be ended with a Stop condition. the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master 4.4 Data Valid (D) must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been The state of the data line represents valid data when, clocked out of the slave. In this case, the slave must after a Start condition, the data line is stable for the leave the data line high to enable the master to generate duration of the high period of the clock signal. the Stop condition (Figure4-2). FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS (A) (B) (C) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point allowing Receiver must release the SDA line at this the Receiver to pull the SDA line low to acknowledge the point so the Transmitter can continue previous eight bits of data. sending data. DS21210K-page 6 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit A control byte is the first byte received following the Start condition from the master device (Figure5-1). The control byte consists of a four-bit control code. For Chip Select Control Code Bits the 24AA024/24LC024/24AA025/24LC025, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits S 1 0 1 0 A2 A1 A0 R/W ACK (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA024/24LC024/24AA025/24LC025 Slave Address devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control Start Bit Acknowledge Bit byte must correspond to the logic levels on the corre- sponding A2, A1 and A0 pins for the device to respond. 5.1 Contiguous Addressing Across These bits are in effect the three Most Significant bits of the word address. Multiple Devices The last bit of the control byte defines the operation to The Chip Select bits A2, A1 and A0 can be used to be performed. When set to a one, a read operation is expand the contiguous address space for up to 16K bits selected. When set to a zero, a write operation is by adding up to eight 24AA024/24LC024/24AA025/ selected. Following the Start condition, the 24AA024/ 24LC025 devices on the same bus. In this case, soft- 24LC024/24AA025/24LC025 monitors the SDA bus ware can use A0 of the control byte as address bit A8, checking the control byte being transmitted. Upon A1 as address bit A9 and A2 as address bit A10. It is receiving a ‘1010’ code and appropriate Chip Select not possible to sequentially read across device bits, the slave device outputs an Acknowledge signal boundaries. on the SDA line. Depending on the state of the R/W bit, the 24AA024/24LC024/24AA025/24LC025 will select a read or write operation. © 2007 Microchip Technology Inc. DS21210K-page 7

24AA024/24LC024/24AA025/24LC025 6.0 WRITE OPERATIONS The higher-order four bits of the word address remain constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the 6.1 Byte Write address counter will roll over and the previously Following the Start signal from the master, the device received data will be overwritten. As with the byte-write code(4 bits), the Chip Select bits (3 bits) and theR/W operation, once the Stop condition is received, an bit (which is a logic-low) is placed onto the bus by the internal write cycle will begin (Figure6-2). If an attempt master transmitter. The device will acknowledge this is made to write to the protected portion of the array control byte during the ninth clock pulse. The next byte when the hardware write protection has been enabled, transmitted by the master is the word address and will the device will acknowledge the command, but no data be written into the Address Pointer of the 24AA024/ will be written. The write cycle time must be observed 24LC024/24AA025/24LC025. After receiving another even if write protection is enabled. Acknowledge signal from the 24AA024/24LC024/ 24AA025/24LC025, the master device will transmit the Note: Page write operations are limited to writing data word to be written into the addressed memory bytes within a single physical page, location. The 24AA024/24LC024/24AA025/24LC025 regardless of the number of bytes acknowledges again and the master generates a Stop actually being written. Physical page condition. This initiates the internal write cycle and, dur- boundaries start at addresses that are ing this time, the 24AA024/24LC024/24AA025/ integer multiples of the page buffer size (or 24LC025 will not generate Acknowledge signals ‘page size’) and end at addresses that are (Figure6-1). If an attempt is made to write to the integer multiples of [page size – 1]. If a protected portion of the array when the hardware write Page Write command attempts to write protection (24XX024 only) has been enabled, the across a physical page boundary, the device will acknowledge the command, but no data will result is that the data wraps around to the be written. The write cycle time must be observed even beginning of the current page (overwriting if write protection is enabled. data previously stored there), instead of being written to the next page, as might be 6.2 Page Write expected. It is therefore necessary for the application software to prevent page write The write control byte, word address and the first data operations that would attempt to cross a byte are transmitted to the 24AA024/24LC024/ page boundary. 24AA025/24LC025 in the same way as in a byte write. However, instead of generating a Stop condition, the 6.3 Write Protection master transmits up to 15 additional data bytes to the 24AA024/24LC024/24AA025/24LC025, which are The WP pin (available on 24XX024 only) must be tied temporarily stored in the on-chip page buffer and will be to VCC or VSS. If tied to VCC, the entire array will be written into the memory once the master has transmit- write-protected. If the WP pin is tied to VSS, write operations to all address locations are allowed. ted a Stop condition. Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by one. FIGURE 6-1: BYTE WRITE S S T BUS ACTIVITY Control Word T MASTER AR Byte Address Data O P T SDA LINE S P A A A BUS ACTIVITY C C C K K K FIGURE 6-2: PAGE WRITE S BUS ACTIVITY T S MASTER A Control Word T R Byte Address (n) Data (n) Data (n +1) Data (n + 15) O T P SDA LINE S P A A A A A BUS ACTIVITY C C C C C K K K K K DS21210K-page 8 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus Send throughput). Once the Stop condition for a Write Write Command command has been issued from the master, the device initiates the internally-timed write cycle, with ACK polling being initiated immediately. This involves the Send Stop master sending a Start condition followed by the control Condition to byte for a Write command (R/W = 0). If the device is still Initiate Write Cycle busy with the write cycle, no ACK will be returned. If no ACK is returned, the Start bit and control byte must be re-sent. If the cycle is complete, the device will return Send Start the ACK and the master can then proceed with the next Read or Write command. See Figure7-1 for a flow diagram of this operation. Send Control Byte with R/W = 0 Did Device No Acknowledge (ACK = 0)? Yes Next Operation © 2007 Microchip Technology Inc. DS21210K-page 9

24AA024/24LC024/24AA025/24LC025 8.0 READ OPERATIONS 8.3 Sequential Read Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a operations, with the exception that the R/W bit of the random read except that after the 24AA024/24LC024/ slave address is set to ‘1’. There are three basic types 24AA025/24LC025 transmits the first data byte, the of read operations: current address read, random read master issues an acknowledge (as opposed to a Stop and sequential read. condition in a random read). This directs the 24AA024/ 24LC024/24AA025/24LC025 to transmit the next 8.1 Current Address Read sequentially-addressed 8-bit word (Figure8-3). To provide sequential reads, the 24AA024/24LC024/ The 24AA024/24LC024/24AA025/24LC025 contains 24AA025/24LC025 contains an internal Address an address counter that maintains the address of the Pointer that is incremented by one upon completion of last word accessed, internally incremented by one. each operation. This Address Pointer allows the entire Therefore, if the previous read access was to address memory contents to be serially read during one n, the next current address read operation would operation. The internal Address Pointer will access data from address n + 1. Upon receipt of the automatically roll over from address 0FFh to address slave address with the R/W bit set to ‘1’, the 24AA024/ 000h. 24LC024/24AA025/24LC025 issues an acknowledge and transmits the 8-bit data word. The master will not FIGURE 8-1: CURRENT ADDRESS acknowledge the transfer, but does generate a Stop READ condition and the 24AA024/24LC024/24AA025/ 24LC025 discontinues transmission (Figure8-1). S T S 8.2 Random Read BUS ACTIVITYA Control T MASTER R Byte Data O T P Random read operations allow the master to access SDA LINE S P any memory location in a random manner. To perform this type of read operation, the word address must first A N be set. This is accomplished by sending the word BUS ACTIVITY C O K A address to the 24AA024/24LC024/24AA025/24LC025 C as part of a write operation. Once the word address is K sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24AA024/24LC024/24AA025/ 24LC025 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowl- edge the transfer but does generate a Stop condition and the 24AA024/24LC024/24AA025/24LC025 discontinues transmission (Figure8-2). After this command, the internal address counter will point to the address location following the one that was just read. DS21210K-page 10 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 FIGURE 8-2: RANDOM READ S S T T S BUS ACTIVITY A Control Word A Control T MASTER R Byte Address (n) R Byte Data (n) O T T P S S P SDA LINE A A A N C C C O BUS ACTIVITY K K K A C K FIGURE 8-3: SEQUENTIAL READ S BUS ACTIVITY Control T MASTER Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x) O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K © 2007 Microchip Technology Inc. DS21210K-page 11

24AA024/24LC024/24AA025/24LC025 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC024 T/XXXNNN I/P e 3 13F YYWW 0519 8-Lead SOIC (3.90 mm) Example: XXXXXXXT 24LC024I XXXXYYWW SN e 3 0519 NNN 13F 8-Lead TSSOP Example: XXXX 4L24 TYWW I519 NNN 13F 8-Lead MSOP Example: 4L24I XXXXT YWWNNN 51913F 8-Lead 2x3 DFN Example: XXX 2P4 YWW 519 NN 13 DS21210K-page 12 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 1st Line Marking Codes Part Number TSSOP MSOP DFN 24AA024 4A24 4A24T 2P1 24LC024 4L24 4L24T 2P4 24AA025 4A25 4A25T 2R1 24LC025 4L25 4L25T 2R4 Note: T = Temperature grade (I, E) Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. © 2007 Microchip Technology Inc. DS21210K-page 13

24AA024/24LC024/24AA025/24LC025 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L A1 c e eB b1 b Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-018B DS21210K-page 14 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 b h α h c A A2 φ A1 L L1 β Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-057B © 2007 Microchip Technology Inc. DS21210K-page 15

24AA024/24LC024/24AA025/24LC025 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c φ A A2 A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-086B DS21210K-page 16 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c A A2 φ A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1.10 Molded Package Thickness A2 0.75 0.85 0.95 Standoff A1 0.00 – 0.15 Overall Width E 4.90 BSC Molded Package Width E1 3.00 BSC Overall Length D 3.00 BSC Foot Length L 0.40 0.60 0.80 Footprint L1 0.95 REF Foot Angle φ 0° – 8° Lead Thickness c 0.08 – 0.23 Lead Width b 0.22 – 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-111B © 2007 Microchip Technology Inc. DS21210K-page 17

24AA024/24LC024/24AA025/24LC025 8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e b N N L K E E2 EXPOSED PAD NOTE 1 NOTE 1 1 2 2 1 D2 TOP VIEW BOTTOM VIEW A NOTE 2 A3 A1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.50 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 2.00 BSC Overall Width E 3.00 BSC Exposed Pad Length D2 1.30 – 1.75 Exposed Pad Width E2 1.50 – 1.90 Contact Width b 0.18 0.25 0.30 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-123B DS21210K-page 18 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 APPENDIX A: REVISION HISTORY Revision F Corrections to Section 1.0, Electrical Characteristics. Revision G Added part number 24AA025 to document. Correction to Section 1.0, Ambient Temperature. Revision H Added DFN package. Revision J (02/2007) Revised Features section; Revised Pin Function Table; Changed 1.8V to 1.7V, Table 1-1 and Table 1-2; Replaced Package Drawings; Replaced On-line Support page; Revised Product ID section. Revision K (03/2007) Replaced Package Drawings (Rev. AM). © 2007 Microchip Technology Inc. DS21210K-page 19

24AA024/24LC024/24AA025/24LC025 NOTES: DS21210K-page 20 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to (cid:129) Distributor or Representative customers. Accessible by using your favorite Internet (cid:129) Local Sales Office browser, the web site contains the following (cid:129) Field Application Engineer (FAE) information: (cid:129) Technical Support (cid:129) Product Support – Data sheets and errata, (cid:129) Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help (cid:129) General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com (cid:129) Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. DS21210K-page 21

24AA024/24LC024/24AA025/24LC025 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA024/24LC024/24AA025/24LC025 Literature Number: DS21210K Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21210K-page 22 © 2007 Microchip Technology Inc.

24AA024/24LC024/24AA025/24LC025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) 24AA024-I/P: Industrial Temperature, Device Temperature Package 1.7V, PDIP Package Range b) 24AA024-I/SN: Industrial Temperature, 1.7V, SOIC Package Device: 24AA024: 1.7V, 2Kbit Addressable Serial EEPROM with c) 24AA025T-I/ST: Industrial Temperature, WP pin. 1.7V, TSSOP Package, Tape and Reel, 24AA024T:1.7V, 2Kbit Addressable Serial EEPROM no WP (Tape and Reel) with WP pin. 24LC024: 2.5V, 2Kbit Addressable Serial EEPROM with d) 24LC024-I/P: Industrial Temperature, WP pin. 2.5V, PDIP Package 24LC024T:2.5V, 2Kbit Addressable Serial EEPROM e) 24LC024-I/MS: Industrial Temperature, (Tape and Reel) with WP pin. 24AA025: 1.7V, 2Kbit Addressable Serial EEPROM with 2.5V, MSOP Package, Tape and Reel no WP pin. f) 24LC025-T-I/SN: Industrial Temperature, 24AA025T:1.7V, 2Kbit Addressable Serial EEPROM 2.5V, SOIC Package, Tape and Reel, No (Tape and Reel) with no WP pin. WP 24LC025: 2.5V, 2Kbit Addressable Serial EEPROM (Tape and Reel) with no WP pin. 24LC025T:2.5V, 2Kbit Addressable Serial EEPROM (Tape and Reel) with no WP pin. Temperature Range: I = -40°C to +85°C Package: P = Plastic DIP, (300 mil Body), 8-lead SN = Plastic SOIC, (3.90 mm Body) ST = TSSOP, 8-lead MS = MSOP, 8-lead MC = 2x3 DFN, 8-lead © 2007 Microchip Technology Inc. DS21210K-page 23

24AA024/24LC024/24AA025/24LC025 NOTES: DS21210K-page 24 © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PROMATE, PowerSmart, rfPIC, and MICROCHIP MAKES NO REPRESENTATIONS OR SmartShunt are registered trademarks of Microchip WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. DS21210K-page 25

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24AA024H-I/ST 24AA024HT-I/MS 24AA024H-I/SN 24AA024HT-I/SN 24AA024HT-I/ST 24AA024H-I/MS 24AA024H-I/P 24AA024T-I/MC 24AA025T-I/MC