Product Order Technical Tools & Support & Folder Now Documents Software Community SN74LVC1G125-Q1 SGES002D–APRIL2003–REVISEDAUGUST2019 SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output 1 Features 3 Description • AEC-Q100QualifiedWiththeFollowingResults: This bus buffer gate is designed for 1.65-V to 5.5-V 1 V operation. – DeviceTemperatureGrade1: –40°Cto CC +125°CAmbientOperatingTemperature The SN74LVC1G125-Q1 device is a single line driver Range with a 3-state output. The output is disabled when the output-enable(OE)inputishigh. – DeviceHuman-BodyModel(HBM)ESD ClassificationLevel2 The CMOS device has high output drive while maintaining low static power dissipation over a broad – DeviceCharged-DeviceModel(CDM)ESD V operatingrange. ClassificationLevelC5 CC • Availableinthesmall1.45-mm2 The SN74LVC1G125-Q1 device is available in a variety of packages including the small DRY package package(DRY)With0.5-mmPitch withabodysizeof1.45mm× 1.00mm. • Supports5-VV Operation CC • Over-voltagetolerantinputsaccept DeviceInformation(1) voltagesto5.5V DEVICENAME PACKAGE BODYSIZE(NOM) • ProvidesdowntranslationtoVCC 1P1G125QDCKRQ1 SOT-23(5) 2.90mm×1.60mm • Maxtpdof3.7nsat3.3V CLVC1G125QDBVRQ1 SC70(5) 2.00mm×1.25mm • Lowpowerconsumption,10-μAMaxI 1P1G125QDRYRQ1 SON(6) 1.45mm×1.00mm CC • ±24-mAOutputdriveat3.3V (1) For all available packages, see the orderable addendum at theendofthedatasheet. • I supportsliveinsertion,partial-power-down off mode,andback-driveprotection • Latch-upperformanceexceeds100mA PerJESD78,ClassII 2 Applications • QualifiedforAutomotiveApplications • Increasedigitalsignaldrivestrength • Redriveupto100MHzsquarewavesignals • Enableordisableadigitalsignalwithhigh- impedanceoffstate 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC1G125-Q1 SGES002D–APRIL2003–REVISEDAUGUST2019 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram.......................................10 2 Applications........................................................... 1 8.3 FeatureDescription.................................................10 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................10 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 11 9.1 ApplicationInformation............................................11 5 PinConfigurationandFunctions......................... 3 9.2 TypicalApplication .................................................11 6 Specifications......................................................... 4 10 PowerSupplyRecommendations..................... 12 6.1 AbsoluteMaximumRatings .....................................4 11 Layout................................................................... 12 6.2 ESDRatings..............................................................4 6.3 RecommendedOperatingConditions......................5 11.1 LayoutGuidelines.................................................12 6.4 ThermalInformation..................................................5 11.2 LayoutExample....................................................12 6.5 ElectricalCharacteristics...........................................6 12 DeviceandDocumentationSupport................. 13 6.6 SwitchingCharacteristics..........................................6 12.1 ReceivingNotificationofDocumentationUpdates13 6.7 OperatingCharacteristics..........................................6 12.2 CommunityResources..........................................13 6.8 TypicalCharacteristics..............................................7 12.3 Trademarks...........................................................13 7 ParameterMeasurementInformation..................8 12.4 ElectrostaticDischargeCaution............................13 12.5 Glossary................................................................13 8 DetailedDescription............................................ 10 13 Mechanical,Packaging,andOrderable 8.1 Overview.................................................................10 Information........................................................... 13 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(April2008)toRevisionD Page • ChangeddatasheetformattonewTIstandard .................................................................................................................... 1 • AddedDRYpackagetoPinConfigurationandFunctions .................................................................................................... 3 • AddedPinFunctionstable..................................................................................................................................................... 3 • AddedHandlingRatingstable. .............................................................................................................................................. 4 • AddedThermalInformationtable. ......................................................................................................................................... 5 • Added–40°Cto125°CTemperaturerangetoElectricalCharacteristics............................................................................... 6 • AddedDetailedDescriptionsection..................................................................................................................................... 10 • AddedApplicationandImplementationsection. ................................................................................................................. 11 • AddedLayoutsection. ......................................................................................................................................................... 12 2 SubmitDocumentationFeedback Copyright©2003–2019,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 www.ti.com SGES002D–APRIL2003–REVISEDAUGUST2019 5 Pin Configuration and Functions DBVpackage DCKpackage 5-pinSOT-23 5-pinSC70 (TopView) (TopView) OE 1 5 V OE 1 5 V CC CC A 2 A 2 GND 3 4 Y GND 3 4 Y DRYpackage 6-pinSON (TransparentTopView) OE 1 6 VCC A 2 5 N.C. GND 3 4 Y N.C.–Nointernalconnection Seemechanicaldrawingsfordimensions. PinFunctions PIN I/O DESCRIPTION NAME DBV,DCK DRY OE 1 1 Input ActivelowOutputEnableInput A 2 2 Input InputA GND 3 3 — Ground Y 4 4 Output OutputY VCC 5 6 — Positivesupply NC – 5 — Nointernalconnection Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 SGES002D–APRIL2003–REVISEDAUGUST2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T Junctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingis notimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingtable. CC 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perAECQ100-002(1) ±2000 HBMESDClassificationLevel V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perAECQ100-011 ±1000 CDMESDClassificationLevel (1) AECQ100-002indicatesthatHBMstressingshallbeinaccordancewiththeANSI/ESDA/JEDECJS-001specification. 4 SubmitDocumentationFeedback Copyright©2003–2019,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 www.ti.com SGES002D–APRIL2003–REVISEDAUGUST2019 6.3 Recommended Operating Conditions(1) MIN MAX UNIT Operating 1.65 5.5 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V =2.3Vto2.7V 1.7 CC V High-levelinputvoltage V IH V =3Vto3.6V 2 CC V =4.5Vto5.5V 0.7×V CC CC V =1.65Vto1.95V 0.35×V CC CC V =2.3Vto2.7V 0.7 CC V Low-levelinputvoltage V IL V =3Vto3.6V 0.8 CC V =4.5Vto5.5V 0.3×V CC CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent –16 mA OH V =3V CC –24 V =4.5V –24 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent 16 mA OL V =3V CC 24 V =4.5V 24 CC V =1.8V±0.15V,2.5V±0.2V 20 CC Δt/Δv Inputtransitionriseorfallrate V =3.3V±0.3V 10 ns/V CC V =5V±0.5V 5 CC T Operatingfree-airtemperature –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 6.4 Thermal Information SN74LVC1G125-Q1 THERMALMETRIC(1) DBV DCK DRY UNIT 5PINS 5PINS 6PINS RθJA Junction-to-ambientthermalresistance 229 278 439 °C/W RθJC(top) Junction-to-case(top)thermalresistance 164 93 277 °C/W RθJB Junction-to-boardthermalresistance 62 65 271 °C/W ψJT Junction-to-topcharacterizationparameter 44 2 84 °C/W ψJB Junction-to-boardcharacterizationparameter 62 64 271 °C/W RθJC(bot) Junction-to-case(bottom)thermalresistance – – – °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 SGES002D–APRIL2003–REVISEDAUGUST2019 www.ti.com 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) –40°Cto125°C PARAMETER TESTCONDITIONS V UNIT CC MIN TYP(1) MAX I =–100μA 1.65Vto5.5V V –0.1 OH CC I =–4mA 1.65V 1.2 OH I =–8mA 2.3V 1.9 OH V V OH I =–16mA 3V 2.4 OH 3V 2.3 I =–24mA OH 4.5V 3.8 I =100μA 1.65Vto5.5V 0.1 OL I =4mA 1.65V 0.45 OL I =8mA 2.3V 0.3 OL V V OL I =16mA 3V 0.4 OL 3V 0.55 I =24mA OL 4.5V 0.55 AorOE I V =5.5VorGND 0to5.5V ±5 μA I inputs I I V orV =5.5V 0 ±10 μA off I O I V =0to5.5V 3.6V 10 μA OZ O I V =5.5VorGND, I =0 1.65Vto5.5V 10 μA CC I O OneinputatV –0.6V, ΔI CC 3Vto5.5V 500 μA CC OtherinputsatV orGND CC C V =V orGND 3.3V 4 pF I I CC (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A 6.6 Switching Characteristics overrecommendedoperatingfree-airtemperaturerangeof–40°Cto125°C,C =50pF(unlessotherwisenoted) L (seeFigure3) V =3.3V V =5V CC CC PARAMETER FROM TO ±0.3V ±0.5V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX t A Y 1 5.1 1 4.1 ns pd t OE Y 1 6 1 5 ns en t OE Y 1 5 1 4.2 ns dis 6.7 Operating Characteristics T =25°C A TEST VCC=3.3V VCC=5V PARAMETER UNIT CONDITIONS TYP TYP Powerdissipation Outputsenabled 19 21 C f=10MHz pF pd capacitance Outputsdisabled 2 4 6 SubmitDocumentationFeedback Copyright©2003–2019,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 www.ti.com SGES002D–APRIL2003–REVISEDAUGUST2019 6.8 Typical Characteristics 2.5 5 TPD TPD 2 4 s 1.5 s 3 n n D - D - P P T 1 T 2 0.5 1 0 0 -100 -50 0 50 100 150 0 1 2 3 4 5 6 Temperature - °C Vcc - V D001 D002 Figure1.TPDAcrossTemperatureat3.3VV Figure2.TPDAcrossV at25°C CC CC Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 SGES002D–APRIL2003–REVISEDAUGUST2019 www.ti.com 7 Parameter Measurement Information V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 15 pF 1 MW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 15 pF 1 MW 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 15 pF 1 MW 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 15 pF 1 MW 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©2003–2019,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 www.ti.com SGES002D–APRIL2003–REVISEDAUGUST2019 Parameter Measurement Information (continued) V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 30 pF 1 kW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 30 pF 500W 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 50 pF 500W 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 50 pF 500W 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure4. LoadCircuitandVoltageWaveforms Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 SGES002D–APRIL2003–REVISEDAUGUST2019 www.ti.com 8 Detailed Description 8.1 Overview The SN74LVC1G125-Q1 device contains one buffer gate device with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using I . The I off off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. 8.2 Functional Block Diagram 8.3 Feature Description • Wideoperatingvoltagerange – Operatesfrom1.65Vto5.5V • Allowsdownvoltagetranslation • Inputsacceptvoltagesto5.5V • I featureallowsvoltagesontheinputsandoutputs,whenV is0V off CC 8.4 Device Functional Modes Table1.FunctionTable INPUTS OUTPUT OE A Y L H H L L L H X Z 10 SubmitDocumentationFeedback Copyright©2003–2019,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 www.ti.com SGES002D–APRIL2003–REVISEDAUGUST2019 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74LVC1G125-Q1 device is a high drive CMOS device that can be used as a output enabled buffer with a high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowingittotranslatedowntoV . CC 9.2 Typical Application Buffer Function Basic LED Driver VCC VCC uC or Logic uC or Logic Wired OR uC or Logic uC or Logic uC or Logic LVC1G125 LVC1G125 Figure5. TypicalApplicationSchematic 9.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloadssoroutingandloadconditionsshouldbeconsideredtopreventringing. 9.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Risetimeandfalltimespecs.See(Δt/ΔV)intheRecommendedOperatingConditionstable. – Specifiedhighandlowlevels.See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputs are overvoltage tolerant allowing them to go as high as (V max) in the Recommended Operating I ConditionstableatanyvalidV . CC 2. RecommendOutputConditions – Load currents should not exceed (I max) per output and should not exceed (Continuous current through O V orGND)totalcurrentforthepart.TheselimitsarelocatedintheAbsoluteMaximumRatings table. CC Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 SGES002D–APRIL2003–REVISEDAUGUST2019 www.ti.com Typical Application (continued) – OutputsshouldnotbepulledaboveV . CC 9.2.3 ApplicationCurves 10 Icc 1.8V 9 Icc 2.5V 8 Icc 3.3V Icc 5V 7 6 A m c - 5 Ic 4 3 2 1 0 0 20 40 60 80 Frequency - MHz D003 Figure6.I vsFrequency,Squarewaveinputsignal CC 10 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installedasclosetothepowerpinaspossibleforbestresults. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages atthe outside connections result in undefined operational states. Figure 7 shows the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure7. PackageLayout 12 SubmitDocumentationFeedback Copyright©2003–2019,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G125-Q1

SN74LVC1G125-Q1 www.ti.com SGES002D–APRIL2003–REVISEDAUGUST2019 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVC1G125-Q1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 1P1G125QDCKRG4Q1 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CMR & no Sb/Br) 1P1G125QDCKRQ1 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CMR & no Sb/Br) 1P1G125QDRYRQ1 ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 FX & no Sb/Br) CLVC1G125QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C25O & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G125-Q1 : •Catalog: SN74LVC1G125 •Enhanced Product: SN74LVC1G125-EP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 7-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) 1P1G125QDCKRQ1 SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 1P1G125QDRYRQ1 SON DRY 6 5000 180.0 9.5 1.2 1.65 0.7 4.0 8.0 Q1 CLVC1G125QDBVRQ1 SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 1P1G125QDCKRQ1 SC70 DCK 5 3000 202.0 201.0 28.0 1P1G125QDRYRQ1 SON DRY 6 5000 189.0 185.0 36.0 CLVC1G125QDBVRQ1 SOT-23 DBV 5 3000 203.0 203.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G

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