11AA02E48/11AA02E64 ® ™ ™ 2K UNI/O Serial EEPROMs with EUI-48 or EUI-64 Node Identity Device Selection Table Density Page Size Temp. Part Number VCC Range Packages Node Address (bits) (Bytes) Ranges 11AA02E48 2K 1.8V-5.5V 16 I SN, TT EUI-48™ 11AA02E64 2K 1.8V-5.5V 16 I SN, TT EUI-64™ Features Description • Preprogrammed Globally Unique, 48-Bit or 64-Bit The Microchip Technology Inc. Node Address 11AA02E48/11AA02E64 (11AA02EXX(1)) device is a • Compatible with EUI-48™ and EUI-64™ 2Kbit Serial Electrically Erasable PROM. The device is • Single I/O, UNI/O® Serial Interface Bus organized in blocks of x8-bit memory and support the patented(2) single I/O UNI/O® serial bus. By using • Low-Power CMOS Technology: Manchester encoding techniques, the clock and data - 1mA active current, typical are combined into a single, serial bit stream (SCIO), - 1µA standby current, maximum where the clock signal is extracted by the receiver to • 256x8-Bit Organization correctly decode the timing and value of each bit. • Schmitt Trigger Inputs for Noise Suppression Note1: 11AA02EXX is used in this document as • Output Slope Control to Eliminate Ground Bounce a generic part number for the 11AA02E48 • 100kbps Maximum Bit Rate – Equivalent to and 11AA02E64 devices. 100kHz Clock Frequency 2: Microchip’s UNI/O® Bus products are • Self-Timed Write Cycle (including Auto-Erase) covered by the following patents issued • Page-Write Buffer for up to 16 Bytes in the U.S.A.: 7,376,020 and 7,788,430. • STATUS Register for Added Control: - Write Enable Latch bit Low-voltage design permits operation down to 1.8V, - Write-In-Progress bit with standby and active currents of only 1µA and 1mA, respectively. • Block Write Protection: - Protect none, 1/4, 1/2 or all of array The 11AA02EXX is available in standard 8-lead SOIC and 3-lead SOT-23 packages. • Built-in Write Protection: - Power-on/off data protection circuitry Package Types (not to scale) - Write enable latch • High Reliability: 3-Lead SOT-23 SOIC - Endurance: 1,000,000 erase/write cycles (TT) (SN) - Data retention: >200 years - ESD protection: >4,000V 2 VCC NC 1 8 VCC • 3-Lead SOT-23 and 8-Lead SOIC Packages VSS 3 NC 2 7 NC NC 3 6 NC • Pb-Free and RoHS Compliant 1 SCIO • Available Temperature Ranges: VSS 4 5 SCIO - Industrial (I): -40°C to +85°C Pin Function Table Name Function SCIO Serial Clock, Data Input/Output VSS Ground VCC Supply Voltage  2008-2018 Microchip Technology Inc. DS20002122E-page 1

11AA02E48/11AA02E64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V SCIO w.r.t. VSS.....................................................................................................................................-0.6V to VCC+1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias.................................................................................................................-40°C to 85°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C VCC = 1.8V to 2.5V TA = -20°C to +85°C Param. Symbol Characteristic Min. Max. Units Test Conditions No. D1 VIH High-Level Input 0.7VCC VCC+1 V Voltage D2 VIL Low-Level Input -0.3 0.3VCC V VCC≥2.5V Voltage -0.3 0.2VCC V VCC<2.5V D3 VHYS Hysteresis of Schmitt 0.05Vcc — V VCC≥2.5V (Note1) Trigger Inputs (SCIO) D4 VOH High-Level Output VCC -0.5 — V IOH=-300µA, VCC=5.5V Voltage VCC -0.5 — V IOH=-200µA, Vcc=2.5V D5 VOL Low-Level Output — 0.4 V IOI=300µA, VCC=5.5V Voltage — 0.4 V IOI=200µA, Vcc=2.5V D6 IO Output Current Limit — ±4 mA VCC = 5.5V (Note1) (Note2) — ±3 mA Vcc = 2.5V (Note1) D7 ILI Input Leakage — ±1 µA VIN = VSS or VCC Current (SCIO) D8 CINT Internal Capacitance — 7 pF TA = 25°C, FCLK = 1MHz, (all inputs and VCC = 5.0V (Note1) outputs) D9 ICCREAD Read Operating — 3 mA VCC=5.5V, FBUS=100kHz, Current CB=100pF — 1 mA VCC=2.5V, FBUS=100kHz, CB=100pF D10 ICCWRITE Write Operating — 5 mA VCC=5.5V Current — 3 mA VCC=2.5V D11 Iccs Standby Current — 1 µA VCC=5.5V, TA=85°C D12 ICCI Idle Mode Current — 50 µA VCC=5.5V Note 1: This parameter is periodically sampled and not 100% tested. 2: The SCIO output driver impedance will vary to ensure IO is not exceeded.  2008-2018 Microchip Technology Inc. DS20002122E-page 2

11AA02E48/11AA02E64 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C VCC = 1.8V to 2.5V TA = -20°C to +85°C Param. Symbol Characteristic Min. Max. Units Test Conditions No. 1 FBUS Serial Bus 10 100 kHz Frequency 2 TE Bit Period 10 100 µs 3 TIJIT Input Edge Jitter — ±0.06 UI Note2 Tolerance 4 FDRIFT Serial Bus — ±0.50 % per byte Frequency Drift Rate Tolerance 5 FDEV Serial Bus — ±5 % per command Frequency Drift Limit 6 TOJIT Output Edge Jitter — ±0.25 UI Note2 7 TR SCIO Input Rise — 100 ns Time (Note1) 8 TF SCIO Input Fall Time — 100 ns (Note1) 9 TSTBY Standby Pulse Time 600 — µs 10 TSS Start Header Setup 10 — µs Time 11 THDR Start Header Low 5 — µs Pulse Time 12 TSP Input Filter Spike — 50 ns Note1 Suppression (SCIO) 13 TWC Write Cycle Time — 5 ms Write, WRSR commands (byte or page) 10 ms ERAL, SETAL commands 14 Endurance (per 1M — cycles 25°C, VCC=5.5V (Note3) page) Note 1: This parameter is periodically sampled and not 100% tested. 2: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained on Microchip’s website: www.microchip.com. TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V VHI = VCC - 0.2V CL = 100 pF Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC  2008-2018 Microchip Technology Inc. DS20002122E-page 3

11AA02E48/11AA02E64 FIGURE 1-1: BUS TIMING – START HEADER 10 11 2 SCIO Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit FIGURE 1-2: BUS TIMING – DATA 2 7 8 12 SCIO Data ‘0’ Data ‘1’ Data ‘1’ Data ‘0’ FIGURE 1-3: BUS TIMING – STANDBY PULSE 9 SCIO Standby Mode FIGURE 1-4: BUS TIMING – JITTER 2 2 3 3 6 6 6 6 Ideal Edge Ideal Edge Ideal Edge Ideal Edge from Master from Master from Slave from Slave  2008-2018 Microchip Technology Inc. DS20002122E-page 4

11AA02E48/11AA02E64 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 11AA02EXX family of serial EEPROMs support the UNI/O® protocol. They can be interfaced with microcontrollers, including Microchip’s PIC® microcontrollers, ASICs, or any other device with an available discrete I/O line that can be configured properly to match the UNI/O protocol. The 11AA02EXX devices contain an 8-bit instruction register. The devices are accessed via the SCIO pin. Data is embedded into the I/O stream through Manchester encoding. The bus is controlled by a master device which determines the clock period, controls the bus access and initiates all operations, while the 11AA02EXX works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is active. FIGURE 2-1: BLOCK DIAGRAM STATUS HV Generator Register EEPROM I/O Control Memory X Control Array Logic Logic Dec Page Latches Current- Limited Slope Control Y Decoder SCIO Sense Amp. VCC R/W Control VSS  2008-2018 Microchip Technology Inc. DS20002122E-page 5

11AA02E48/11AA02E64 3.0 BUS CHARACTERISTICS If a command is terminated in any manner other than a NoMAK/SAK combination, then the master must 3.1 Standby Pulse perform a standby pulse before beginning a new command, regardless of which device is to be selected When the master has control of SCIO, a standby pulse . can be generated by holding SCIO high for TSTBY. At Note: After a POR/BOR event occurs, a this time, the 11AA02EXX will reset and return to low-to-high transition on SCIO must be Standby mode. Subsequently, a high-to-low transition generated before proceeding with on SCIO (the first low pulse of the header) will return communication, including a standby the device to the active state. pulse. Once a command is terminated satisfactorily (i.e., via a NoMAK/SAK combination during the Acknowledge An example of two consecutive commands is shown in sequence), performing a standby pulse is not required Figure3-1. Note that the device address is the same to begin a new command as long as the device to be for both commands, indicating that the same device is selected is the same device selected during the being selected both times. previous command. However, a period of TSS must be A standby pulse cannot be generated while the slave observed after the end of the command and before the has control of SCIO. In this situation, the master must beginning of the start header. After TSS, the start wait for the slave to finish transmitting and to release header (including THDR low pulse) can be transmitted SCIO before the pulse can be generated. in order to begin the new command. If, at any point during a command, an error is detected by the master, a standby pulse should be generated and the command should be performed again. FIGURE 3-1: CONSECUTIVE COMMANDS EXAMPLE K A Standby Pulse(1) Start Header AK oS Device Address AK AK M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K A K A oM AK SS Start Header AK oS Device Address AK AK N S T M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 Note1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first standby pulse. 3.2 Start Data Transfer When a standby pulse is not required (i.e., between successive commands to the same device), a period of All operations must be preceded by a start header. The TSS must be observed after the end of the command start header consists of holding SCIO low for a period and before the beginning of the start header. of THDR, followed by transmitting an 8-bit ‘01010101’ Figure3-2 shows the waveform for the start header, code. This code is used to synchronize the slave’s including the required Acknowledge sequence at the internal clock period with the master’s clock period, so end of the byte. accurate timing is very important. FIGURE 3-2: START HEADER SCIO TSS THDR Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK NoSAK  2008-2018 Microchip Technology Inc. DS20002122E-page 6

11AA02E48/11AA02E64 3.3 Acknowledge FIGURE 3-4: ACKNOWLEDGE BITS An Acknowledge routine occurs after each byte is MAK (‘1’) SAK (‘1’) transmitted, including the start header. This routine consists of two bits. The first bit is transmitted by the master, and the second bit is transmitted by the slave. Note: A MAK must always be transmitted NoMAK (‘0’) NoSAK(1) following the start header. The Master Acknowledge, or MAK, is signified by transmitting a ‘1’, and informs the slave that the current operation is to be continued. Conversely, a Not Note 1: A NoSAK is defined as any sequence that is not a Acknowledge, or NoMAK, is signified by transmitting a valid SAK. ‘0’, and is used to end the current operation (and initiate the write cycle for write operations). 3.4 Device Addressing Note: When a NoMAK is used to end a WRITE or A device address byte is the first byte received from the WRSR instruction, the write cycle is not master device following the start header. The device initiated if no bytes of data have been address byte consists of a four-bit family code, for the received. 11AA02EXX this is set as ‘1010’. The last four bits of the device address byte are the device code, which is The slave Acknowledge, or SAK, is also signified by hardwired to ‘0000’. transmitting a ‘1’, and confirms proper communication. However, unlike the NoMAK, the NoSAK is signified by FIGURE 3-5: DEVICE ADDRESS BYTE the lack of a middle edge during the bit period. ALLOCATION Note: In order to guard against bus contention, a SLAVE ADDRESS MAKSAK NoSAK will occur after the start header. A NoSAK will occur for the following events: • Following the start header 1 0 1 0 0 0 0 0 • Following the device address, if no slave on the bus matches the transmitted address • Following the command byte, if the command is 3.5 Bus Conflict Protection invalid, including Read, CRRD, Write, WRSR, SETAL, and ERAL during a write cycle. To help guard against high-current conditions arising from bus conflicts, the 11AA02EXX features a • If the slave becomes out of sync with the master current-limited output driver. The IOL and IOH • If a command is terminated prematurely by using specifications describe the maximum current that can a NoMAK, with the exception of immediately after be sunk or sourced, respectively, by the SCIO pin. The the device address. 11AA02EXX will vary the output driver impedance to See Figure3-3 and Figure3-4 for details. ensure that the maximum current level is not exceeded. If a NoSAK is received from the slave after any byte (except the start header), an error has occurred. The master should then perform a standby pulse and begin the desired command again. FIGURE 3-3: ACKNOWLEDGE ROUTINE Master Slave MAK SAK  2008-2018 Microchip Technology Inc. DS20002122E-page 7

11AA02E48/11AA02E64 3.6 Device Standby There are two variables which can cause the 11AA02EXX to lose synchronization. The first is The 11AA02EXX features a low-power Standby mode frequency drift, defined as a change in the bit during which the device is waiting to begin a new period,TE. The second is edge jitter, which is a single command. A high-to-low transition on SCIO will exit occurrence change in the position of an edge within a low-power mode and prepare the device for receiving bit period, while the bit period itself remains constant. the start header. 3.8.1 FREQUENCY DRIFT Standby mode will be entered upon the following conditions: Within a system, there is a possibility that frequencies • A NoMAK followed by a SAK can drift due to changes in voltage, temperature, etc. (i.e., valid termination of a command) The re-synchronization circuitry provides some • Reception of a standby pulse tolerance for such frequency drift. The tolerance range is specified by two parameters, FDRIFT and FDEV. FDRIFT specifies the maximum tolerable change in bus Note: In the case of the WRITE, WRSR, SETAL, frequency per byte. FDEV specifies the overall limit in or ERAL commands, the write cycle is frequency deviation within an operation (i.e., from the initiated upon receipt of the NoMAK, end of the start header until communication is assuming all other write requirements terminated for that operation). The start header at the have been met. beginning of the next operation will reset the 3.7 Device Idle re-synchronization circuitry and allow for another FDEV amount of frequency drift. The 11AA02EXX features an Idle mode during which 3.8.2 EDGE JITTER all serial data is ignored until a standby pulse occurs. Idle mode will be entered upon the following Ensuring that edge transitions from the master always conditions: occur exactly in the middle or end of the bit period is not • Invalid device address always possible. Therefore, the re-synchronization circuitry is designed to provide some tolerance for edge • Invalid command byte, including Read, CRRD, jitter. Write, WRSR, SETAL and ERAL during a write cycle The 11AA02EXX adjusts its phase every MAK bit, so • Missed edge transition TIJIT specifies the maximum allowable peak-to-peak jitter relative to the previous MAK bit. Since the position • Reception of a MAK following a WREN, WRDI, of the previous MAK bit would be difficult to measure by SETAL, or ERAL command byte the master, the minimum and maximum jitter values for • Reception of a MAK following the data byte of a a system should be considered the worst-case. These WRSR command values will be based on the execution time for different An invalid start header will indirectly cause the device branch paths in software, jitter due to thermal noise, to enter Idle mode. Whether or not the start header is etc. invalid cannot be detected by the slave, but will The difference between the minimum and maximum prevent the slave from synchronizing properly with the values, as a percentage of the bit period, should be master. If the slave is not synchronized with the calculated and then compared against TIJIT to master, an edge transition will be missed, thus causing determine jitter compliance. the device to enter Idle mode. Note: Because the 11AA02EXX only 3.8 Synchronization re-synchronizes during the MAK bit, the At the beginning of every command, the 11AA02EXX overall ability to remain synchronized utilizes the start header to determine the master’s bus depends on a combination of frequency clock period. This period is then used as a reference for drift and edge jitter (i.e., if the MAK bit all subsequent communication within that command. edge is experiencing the maximum allowable edge jitter, then there is no room The 11AA02EXX features re-synchronization circuitry for frequency drift). Conversely, if the which will monitor the position of the middle data edge frequency has drifted to the maximum during each MAK bit and subsequently adjust the amount tolerable within a byte, then no internal time reference in order to remain synchronized edge jitter can be present. with the master.  2008-2018 Microchip Technology Inc. DS20002122E-page 8

11AA02E48/11AA02E64 4.0 DEVICE COMMANDS After the device address byte, a command byte must be sent by the master to indicate the type of operation to be performed. The code for each instruction is listed in Table4-1. TABLE 4-1: INSTRUCTION SET Instruction Name Instruction Code Hex Code Description READ 0000 0011 0x03 Read data from memory array beginning at specified address CRRD 0000 0110 0x06 Read data from current location in memory array WRITE 0110 1100 0x6C Write data to memory array beginning at specified address WREN 1001 0110 0x96 Set the write enable latch (enable write operations) WRDI 1001 0001 0x91 Reset the write enable latch (disable write operations) RDSR 0000 0101 0x05 Read STATUS register WRSR 0110 1110 0x6E Write STATUS register ERAL 0110 1101 0x6D Write ‘0x00’ to entire array SETAL 0110 0111 0x67 Write ‘0xFF’ to entire array 4.1 Read Instruction To provide sequential reads in this manner, the 11AA02EXX contains an internal Address Pointer The Read command allows the master to access any which is incremented by one after the transmission of memory location in a random manner. After the READ each byte. This Address Pointer allows the entire instruction has been sent to the slave, the two bytes of memory contents to be serially read during one the Word Address are transmitted, with an operation. When the highest address is reached, the Acknowledge sequence being performed after each Address Pointer rolls over to address ‘0x00’ if the byte. Then, the slave sends the first data byte to the master chooses to continue the operation by providing master. If more data is to be read, the master sends a a MAK. MAK, indicating that the slave should output the next data byte. This continues until the master sends a NoMAK, which ends the operation. FIGURE 4-1: READ COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K K K K K K Command A A Word Address MSB A A Word Address LSB A A M S M S M S SCIO 151413121110 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 K A K K K K M K Data Byte 1 A A Data Byte 2 A A Data Byte n o A M S M S N S SCIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2008-2018 Microchip Technology Inc. DS20002122E-page 9

11AA02E48/11AA02E64 4.2 Current Address Read (CRRD) TABLE 4-2: INTERNAL ADDRESS Instruction COUNTER The internal address counter featured on the Command Event Action 11AA02EXX maintains the address of the last memory — Power-on Reset Counter is undefined array location accessed. The CRRD instruction allows READ or MAK edge Counter is updated the master to read data back beginning from this WRITE following each with newly received current location. Consequently, no word address is Address byte value provided upon issuing this command. READ, MAK/NoMAK Counter is Note that, except for the initial word address, the READ WRITE, or edge following incremented by 1 and CRRD instructions are identical, including the CRRD each data byte ability to continue requesting data through the use of MAKs in order to sequentially read from the array. Note: If, following each data byte in a READ, As with the READ instruction, the CRRD instruction is WRITE, or CRRD instruction, neither a terminated by transmitting a NoMAK. MAK nor a NoMAK edge is received Table4-2 lists the events upon which the internal (i.e., if a standby pulse occurs instead), address counter is modified. the internal address counter will not be incremented. Note: During a Write command, once the last data byte for a page has been loaded, the internal Address Pointer will rollover to the beginning of the selected page. FIGURE 4-2: CRRD COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K K K K K K Command A A Data Byte 1 A A Data Byte 2 A A M S M S M S SCIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 K A M K Data Byte n o A N S SCIO 7 6 5 4 3 2 1 0  2008-2018 Microchip Technology Inc. DS20002122E-page 10

11AA02E48/11AA02E64 4.3 Write Instruction Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by one. Prior to any attempt to write data to the 11AA02EXX, The higher-order bits of the word address remain the write enable latch must be set by issuing the WREN constant. If the master should transmit data past the instruction (see Section4.4 “Write Enable (WREN) end of the page, the address counter will roll over to the and Write Disable (WRDI) Instructions”). beginning of the page, where further received data will Once the write enable latch is set, the user may be written. proceed with issuing a WRITE instruction (including the Note: Page write operations are limited to header and device address bytes) followed by the MSB writing bytes within a single physical page, and LSB of the Word Address. Once the last regardless of the number of bytes Acknowledge sequence has been performed, the actually being written. Physical page master transmits the data byte to be written. boundaries start at addresses that are The 11AA02EXX features a 16-byte page buffer, integer multiples of the page size meaning that up to 16 bytes can be written at one time. (16bytes) and end at addresses that are To utilize this feature, the master can transmit up to integer multiples of the page size minus 1. 16data bytes to the 11AA02EXX, which are As an example, the page that begins at temporarily stored in the page buffer. After each data address 0x30 ends at address 0x3F. If a byte, the master sends a MAK, indicating whether or page Write command attempts to write not another data byte is to follow. A NoMAK indicates across a physical page boundary, the that no more data is to follow, and as such will initiate result is that the data wraps around to the the internal write cycle. beginning of the current page (overwriting data previously stored there), instead of Note: If a NoMAK is generated before any data being written to the next page as might be has been provided, or if a standby pulse expected. It is therefore necessary for the occurs before the NoMAK is generated, application software to prevent page write the 11AA02EXX will be reset, and the operations that would attempt to cross a write cycle will not be initiated. page boundary. FIGURE 4-3: WRITE COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K K K K K K Command A A Word Address MSB A A Word Address LSB A A M S M S M S SCIO 151413121110 9 8 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 K A M K K K K K Data Byte 1 A A Data Byte 2 A A Data Byte n o A M S M S N S SCIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Twc  2008-2018 Microchip Technology Inc. DS20002122E-page 11

11AA02E48/11AA02E64 4.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) Instructions write enable latch will be reset: • Power-up The 11AA02EXX contains a write enable latch. See • WRDI instruction successfully executed Table6-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI instruction will reset the latch. • ERAL instruction successfully executed • SETAL instruction successfully executed Note: The WREN and WRDI instructions must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command. FIGURE 4-4: WRITE ENABLE COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K A M K Command o A N S SCIO 1 0 0 1 0 1 1 0 FIGURE 4-5: WRITE DISABLE COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K A M K Command o A N S SCIO 1 0 0 1 0 0 0 1  2008-2018 Microchip Technology Inc. DS20002122E-page 12

11AA02E48/11AA02E64 4.5 Read Status Register (RDSR) The Block Protection (BP0 and BP1) bits indicate Instruction which blocks are currently write-protected. These bits are set by the user through the WRSR instruction. These The RDSR instruction provides access to the STATUS bits are nonvolatile. register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is Note: If Read Status Register command is formatted as follows: initiated while the 11AA02EXX is currently executing an internal write cycle on the 7 6 5 4 3 2 1 0 STATUS register, the new Block X X X X BP1 BP0 WEL WIP Protection bit values will be read during Note: Bits 4-7 are don’t cares, and will read as ‘0’. the entire command. The Write-In-Process (WIP) bit indicates whether the The WIP and WEL bits will update dynamically 11AA02EXX is busy with a write operation. When set to (asynchronous to issuing the RDSR instruction). a ‘1’, a write is in progress, when set to a ‘0’, no write is Furthermore, after the STATUS register data is in progress. This bit is read-only. received, the master can provide a MAK during the Acknowledge sequence to request that the data be The Write Enable Latch (WEL) bit indicates the status transmitted again. This allows the master to of the write enable latch. When set to a ‘1’, the latch continuously monitor the WIP and WEL bits without the allows writes to the array, when set to a ‘0’, the latch need to issue another full command. prohibits writes to the array. This bit is set and cleared using the WREN and WRDI instructions, respectively. Once the master is finished, it provides a NoMAK to This bit is read-only for any other instruction. end the operation. Note: The current drawn for a Read Status Register command during a write cycle is a combination of the ICC Read and ICC Write operating currents. FIGURE 4-6: READ STATUS REGISTER COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K A K K M K Command A A STATUS Register Data o A M S N S SCIO 3 2 1 0 0 0 0 0 0 1 0 1 0 0 0 0 Note: The STATUS register data can continuously be read or polled by transmitting a MAK in place of the NoMAK.  2008-2018 Microchip Technology Inc. DS20002122E-page 13

11AA02E48/11AA02E64 4.6 Write Status Register (WRSR) TABLE 4-3: ARRAY PROTECTION Instruction Array Addresses BP1 BP0 Write-Protected The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the 0 0 none appropriate bits in the STATUS register. The array is 0 1 upper 1/4 divided up into four segments. The user has the ability (C0h-FFh) to write-protect none, one, two, or all four of the 1 0 upper 1/2 segments of the array. The partitioning is controlled as (80h-FFh) illustrated in Table4-3. 1 1 all After transmitting the STATUS register data, the master (00h-FFh) must transmit a NoMAK during the Acknowledge sequence in order to initiate the internal write cycle. Note: The WRSR instruction must be terminated with a NoMAK following the data byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command. FIGURE 4-7: WRITE STATUS REGISTER COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K A K K M K Command A A Status Register Data o A M S N S SCIO 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 Twc  2008-2018 Microchip Technology Inc. DS20002122E-page 14

11AA02E48/11AA02E64 4.7 Erase All (ERAL) Instruction The ERAL instruction is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2 or The ERAL instruction allows the user to write ‘0x00’ to all of the array is protected. the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing Note: The ERAL instruction must be terminated the WREN instruction. with a NoMAK following the command Once the write enable latch is set, the user may byte. If a NoMAK is not received at this proceed with issuing a ERAL instruction (including the point, the command will be considered header and device address bytes). Immediately after invalid, and the device will go into Idle the NoMAK bit has been transmitted by the master, the mode without responding with a SAK or internal write cycle is initiated, during which time all executing the command. words of the memory array are written to ‘0x00’. FIGURE 4-8: ERASE ALL COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K A M K Command o A N S SCIO 0 1 1 0 1 1 0 1 Twc 4.8 Set All (SETAL) Instruction The SETAL instruction is ignored if either of the Block Protect bits (BP0, BP1) is not ‘0’, meaning 1/4, 1/2 or The SETAL instruction allows the user to write ‘0xFF’ to all of the array is protected. the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing Note: The SETAL instruction must be terminated the WREN instruction. with a NoMAK following the command Once the write enable latch is set, the user may byte. If a NoMAK is not received at this proceed with issuing a SETAL instruction (including the point, the command will be considered header and device address bytes). Immediately after invalid, and the device will go into Idle the NoMAK bit has been transmitted by the master, the mode without responding with a SAK or internal write cycle is initiated, during which time all executing the command. words of the memory array are written to ‘0xFF’. FIGURE 4-9: SET ALL COMMAND SEQUENCE K A K S K K Standby Pulse Start Header A o Device Address A A M N M S SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 K A M K Command o A N S SCIO 0 1 1 0 0 1 1 1 Twc  2008-2018 Microchip Technology Inc. DS20002122E-page 15

11AA02E48/11AA02E64 5.0 DATA PROTECTION 6.0 POWER-ON STATE The following protection has been implemented to The 11AA02EXX powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Shutdown mode, • The Write Enable Latch (WEL) is reset on requiring a low-to-high transition on SCIO to enter power-up Idle mode • A Write Enable (WREN) instruction must be issued • The Write Enable Latch (WEL) is reset to set the write enable latch • The internal Address Pointer is undefined • After a write, ERAL, SETAL, or WRSR command, • A low-to-high transition, standby pulse and the write enable latch is reset subsequent high-to-low transition on SCIO (the • Commands to access the array or write to the first low pulse of the header) are required to enter status register are ignored during an internal write the active state cycle and programming is not affected . TABLE 6-1: WRITE PROTECT FUNCTIONALITY MATRIX WEL Protected Blocks Unprotected Blocks Status Register 0 Protected Protected Protected 1 Protected Writable Writable  2008-2018 Microchip Technology Inc. DS20002122E-page 16

11AA02E48/11AA02E64 7.0 PREPROGRAMMED EUI-48™ 7.2 EUI-48™ Node Address OR EUI-64™ NODE ADDRESS (11AA02E48) The 11AA02EXX is programmed at the factory with a The 6-byte EUI-48™ node address value of the globally unique node address stored in the upper 1/4 of 11AA02E48 is stored in array locations 0xFA through the array and write-protected through the STATUS 0xFF, as shown in Figure7-2. The first three bytes are register. The remaining 1,536 bits are available for the Organizationally Unique Identifier (OUI) assigned application use. to Microchip by the IEEE Registration Authority. The remaining three bytes are the Extension Identifier, and FIGURE 7-1: MEMORY ORGANIZATION are generated by Microchip to ensure a globally-unique, 48-bit value. 00h 7.2.1 ORGANIZATIONALLY UNIQUE Standard IDENTIFIER (OUI) EEPROM Each OUI provides roughly 16M (224) addresses. Once the address pool for an OUI is exhausted, Microchip C0h will acquire a new OUI from IEEE to use for Write-Protected programming this model. For more information on past Node Address Block FFh and current OUIs see “Organizationally Unique Identifiers For Preprogrammed EUI-48 and EUI-64 7.1 Factory-Programmed Write Address Devices” Technical Brief (DS90003187). Protection Note: The OUI will change as addresses are In order to help guard against accidental corruption of exhausted. Customers are not guaran- the node address, the BP1 and BP0 bits of the STATUS teed to receive a specific OUI and should register are programmed at the factory to ‘0’ and ‘1’, design their application to accept new respectively, as shown in the following table. OUIs as they are introduced. 7 6 5 4 3 2 1 0 7.2.2 EUI-64™ SUPPORT USING THE X X X X BP1 BP0 WEL WIP 11AA02E48 — — — — 0 1 — — The preprogrammed EUI-48 node address of the 11AA02E48 can easily be encapsulated at the This protects the upper 1/4 of the array (0xC0 to 0xFF) application level to form a globally unique, 64-bit node from write operations. This array block can be utilized address for systems utilizing the EUI-64 standard. This for writing by clearing the BP bits with a Write Status is done by adding 0xFFFE between the OUI and the Register (WRSR) instruction. Note that if this is Extension Identifier, as shown below. performed, care must be taken to prevent overwriting the node address value. Note: As an alternative, the 11AA02E64 features an EUI-64 node address that can be used in EUI-64 applications directly without the need for encapsulation, thereby simplifying system software. See Section7.3 “EUI-64™ Node Address (11AA02E64)” for details. 2008-2018 Microchip Technology Inc. DS20002122E-page 17

11AA02E48/11AA02E64 FIGURE 7-2: EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (11AA02E48) 24-bit Organizationally 24-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h Array FAh FFh Address Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56  2008-2018 Microchip Technology Inc. DS20002122E-page 18

11AA02E48/11AA02E64 ™ 7.3 EUI-64 Node Address (11AA02E64) The 8-byte EUI-64™ node address value of the 11AA02E64 is stored in array locations 0xF8 through 0xFF, as shown in Figure7-3. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining five bytes are the Extension Identifier, and are generated by Microchip to ensure a globally-unique, 64-bit value. Note: In conformance with IEEE guidelines, Microchip will not use the values 0xFFFE and 0xFFFF for the first two bytes of the EUI-64 Extension Identifier. These two values are specifically reserved to allow applications to encapsulate EUI-48 addresses into EUI-64 addresses. FIGURE 7-3: EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (11AA02E64) 24-bit Organizationally 40-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h 78h 90h Array F8h FFh Address Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90  2008-2018 Microchip Technology Inc. DS20002122E-page 19

11AA02E48/11AA02E64 8.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table8-1. TABLE 8-1: PIN FUNCTION TABLE Name 3-pin SOT-23 8-pin SOIC Description SCIO 1 5 Serial Clock, Data Input/Output VCC 2 8 Supply Voltage VSS 3 4 Ground NC — 1, 2, 3, 6, 7 No Internal Connection 8.1 Serial Clock, Data Input/Output (SCIO) SCIO is a bidirectional pin used to transfer commands and addresses into, as well as data into and out of the device. The serial clock is embedded into the data stream through Manchester encoding. Each bit is represented by a signal transition at the middle of the bit period.  2008-2018 Microchip Technology Inc. DS20002122E-page 20

11AA02E48/11AA02E64 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead SOIC Example XXXXXXXT 11A2E48I XXXXYYWW SN e 3 1628 NNN 1L7 3-Lead SOT-23 (11AA02E48) Example XXNN E217 3-Lead SOT-23 (11AA02E64) Example XXXNNN AAA1L7 1st Line Marking Code Part Number SOT-23 SOIC 11AA02E48 E2NN 11A2E48T 11AA02E64 AAANNN 11A2E64T Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC® designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2018 Microchip Technology Inc. DS20002122E-page 21

11AA02E48/11AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2008-2018 Microchip Technology Inc. DS20002122E-page 22

11AA02E48/11AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2008-2018 Microchip Technology Inc. DS20002122E-page 23

11AA02E48/11AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2008-2018 Microchip Technology Inc. DS20002122E-page 24

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DS20002122E-page 25

11AA02E48/11AA02E64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2018 Microchip Technology Inc. DS20002122E-page 26

11AA02E48/11AA02E64 APPENDIX A: REVISION HISTORY Revision A (12/2008) Initial release of this document. Revision B (04/2013) Revised AC Characteristic Maximum Parameters 3and 4; Added 11AA02E64 part. Revision C (12/2014) Updated Section7.0 “Preprogrammed EUI-48™ or EUI-64™ Node Address”; Updated Product Identifica- tion System section. Revision D (08/2016) Added new OUI (54-10-EC) to list. Revision E (02/2018) Added detailed description of OUIs.  2008-2018 Microchip Technology Inc. DS20002122E-page 27

11AA02E48/11AA02E64 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, appli- • Technical Support cation notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, representa- documents, latest software releases and archived tive or Field Application Engineer (FAE) for support. software Local sales offices are also available to help custom- ers. A listing of sales offices and locations is included in • General Technical Support – Frequently Asked the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registration instructions.  2008-2018 Microchip Technology Inc. DS20002122E-page 28

11AA02E48/11AA02E64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X]((11)) X /XX Examples: Device Tape and Reel Temperature Package a) 11AA02E48T-I/TT = 2Kbit, 1.8V Serial Option Range EEPROM with EUI-48 Node Iden- tity, Tape & Reel, Device: 11AA02E48 = 2Kbit, 1.8V UNI/O® Serial EEPROM Industrial temp., with EUI-48™ Node Identity SOT-23 package 11AA02E64 = 2 Kbit, 1.8V UNI/O® Serial EEPROM b) 11AA02E48-I/SN = 2Kbit, 1.8V Serial with EUI-64™ Node Identity EEPROM with EUI-48 Node Iden- tity, Industrial temp., Tape and Reel Blank = Standard packaging (tube or tray) Option: T = Tape and Reel(1) SOIC package c) 11AA02E48T-I/SN = 2Kbit, 1.8V Serial EEPROM with Temperature I = -40C to +85C (Industrial) EUI-48 Node Iden- Range: tity, Tape & Reel, Industrial temp., SOIC package Package: SN = 8-lead Plastic SOIC (3.90 mm body) TT = 3-lead SOT-23 (Tape and Reel only) d) 11AA02E64T-I/TT = 2Kbit, 1.8V Serial EEPROM with EUI-64 Node Iden- tity, Tape & Reel, Industrial temp., SOT-23 package e) 11AA02E64-I/SN = 2Kbit, 1.8V Serial EEPROM with EUI-64 Node Iden- tity, Industrial temp., SOIC package f) 11AA02E64T-I/SN = 2Kbit, 1.8V Serial EEPROM with EUI-64 Node Iden- tity, Tape & Reel, Industrial temp., SOIC package Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2008-2018 Microchip Technology Inc. DS20002122E-page 29

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT ensure that your application meets with your specifications. logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, MICROCHIP MAKES NO REPRESENTATIONS OR Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK WARRANTIES OF ANY KIND WHETHER EXPRESS OR MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST IMPLIED, WRITTEN OR ORAL, STATUTORY OR logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 OTHERWISE, RELATED TO THE INFORMATION, logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are QUALITY, PERFORMANCE, MERCHANTABILITY OR registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter- Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Microchip Tempe, Arizona; Gresham, Oregon and design centers in California Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip Technology analog products. In addition, Microchip’s quality system for the design Inc., in other countries. and manufacture of development systems is ISO 9001:2000 certified. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2008-2018, Microchip Technology Incorporated, All Rights Reserved. CERTIFIED BY DNV ISBN: 978-1-5224-2733-9 == ISO/TS 16949 ==  2008-2018 Microchip Technology Inc. DS20002122E-page 30

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 11AA02E48-I/SN 11AA02E48T-I/SN 11AA02E48T-I/TT 11AA02E64T-I/TT 11AA02E64-I/SN 11AA02E64T-I/SN